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1. 发明专利

JPH10163120A VERTICAL BOAT 失效
公开(公告)号：JPH10163120A
公开(公告)日：1998-06-19
申请号：JP31743296
申请日：1996-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MINOWA KIYOUKO , ISOMAE SEIICHI , SUZUKI TADASHI , SHIMIZU HIROBUMI , SATO TOMOMI
IPC分类号： H01L21/683 , H01L21/205 , H01L21/22 , H01L21/31 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To suppress the slip even when large-diameter wafers are heat-treated by being stacked, by mounting quartz-made cylindrical protrusions for horizontally supporting the peripheries of the Si wafers on a jig for a semiconductor vertical diffusion apparatus. SOLUTION: Between a pair of upper and lower circular plates 1, three or more support posts 2 are disposed. Support protrusions 5 made of a quartz material having a lower elastic modulus than that of an Si wafer 5, high heat resistance, high corrosion resistance, high purity and high machining accuracy are incorporated and mounted at specified intervals along the length of the support posts 2. Si wafers 4 are mounted on these protrusions 5 respectively. Because of the softer quartz material of the protrusions 5 than the wafer 4, they scarcely scratch the contacted wafers 4, resulting in that the slip is eliminated when many Si wafers 4 are heat treated en bloc.

2. 发明专利

JPH0982768A EVALUATING METHOD FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH0982768A
公开(公告)日：1997-03-28
申请号：JP23974695
申请日：1995-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SUZUKI NORIO , SHIMIZU HIROBUMI , SUGINO YUSHI
IPC分类号： G01R27/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To make it possible to evaluate the structure and characteristics of a semiconductor wafer by measuring the change of the resistivity caused by a thermal doner generated from interlattice oxygen in the case of annealing the wafer. SOLUTION: The change of the resistivity caused by a thermal doner generated from interlattice oxygen in the case of annealing a semiconductor wafer is measured. For example, an epitaxial wafer that a p-type epitaxial layer is vapor grown on a crystal substrate (100) made of p-type single crystal silicon manufactured by a CZ method is resistance-annealed at 450 deg.C for 60 hours to generate the thermal doner in the substrate. Since the excess thermal doner is generated by the low-temperature annealing, the substrate is inverted from the p-type to the n-type. The resistivity distribution becomes as shown, and the resistivity has a point of inflection (maximum value) at the boundary between the substrate and the epitaxial layer. Accordingly, the thickness of the epitaxial layer can be obtained by knowing the distance from the surface of the epitaxial layer to the point of inflection (maximum value).

3. 发明专利

JPH07221112A MANUFACTURE OF SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH07221112A
公开(公告)日：1995-08-18
申请号：JP1082194
申请日：1994-02-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SUZUKI NORIO
IPC分类号： H01L29/78 , H01L21/322
摘要： PURPOSE:To obtain an Si wafer which is very reliable near the surface of the wafer since it has a non-defect layer near the surface of the wafer and to increase the characteristics of the device such as a gate withstand strength by depositing an a-Si (amorphous silicon) layer in a specified thickness at a specified temperature on the rear face of the Si wafer. CONSTITUTION:First, an Si wafer 1 is prepared. Nextly, due to thermal decomposition of silane (SiH4), an a-Si layer 2 is formed in the thickness of about 1mum at 570-580 deg.C on the rear face of the Si wafer 1 which is a second primary face. When the wafer 1 is heat-treated, crystal defects and an oxygen deposit 6, which exist in the wafer 1, absorb impurities (a gettering action) or extinguish crystal defects due to a grain boundary generated near an interface between the wafer 1 and the a-Si layer 2, a stress of the interface such as crystallization, and a distortion field of dislocation which accompanies the stress of the interface, since the a-Si layer 2 exists on the rear face of the wafer 1.

4. 发明专利

JPH05315320A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05315320A
公开(公告)日：1993-11-26
申请号：JP12031292
申请日：1992-05-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UENISHI TOSHIYA , SUZUKI NORIO , KOSAKA YUJI , NAKAMURA ATSUSHI , SATO TOMOMI
IPC分类号： H01L21/76 , H01L21/316
摘要： PURPOSE:To contrive to enhance gate withstand voltage by a method wherein a bird's beak length of an element isolation oxide film in a semiconductor integrated circuit device is uniformized irrespective of mask patterns and sink of a gate oxide film of a second layer in a two-layer gate structure is removed. CONSTITUTION:A nitrided silicon film 1 is used as a mask and oxygen 4 or silicon 4 is implanted aslant into a silicon substrade 5 through an oxide film 2, thereafter it is heat-treated in an oxidation atmosphere to form the element isolation oxide film 5.

5. 发明专利

JPH05291242A 失效
公开(公告)号：JPH05291242A
公开(公告)日：1993-11-05
申请号：JP9318792
申请日：1992-04-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HATA KAZUHIRO , NAKAMURA ATSUSHI , SATO TOMOMI
IPC分类号： H01L21/316
摘要： PURPOSE:To reduce the removed amount of the upper part of a field insulating film more than that in conventional cases when a pad film is etched and removed in a manufacturing method, of a semiconductor integrated circuit device, wherein an OSELO method is used when the field insulating film for element isolation is formed. CONSTITUTION:In the manufacturing method, of a semiconductor integrated circuit device, wherein the OSELO method is used, the following are used as oxidation masks when a field insulating film for element isolation is formed on a semiconductor substrate 1: a first oxidation-mask film pattern 3a which is formed on the semiconductor substrate 1 and which is composed of Si3N4; and a second oxidation-mask film pattern 5a which is formed on its sidewall side, which is composed of Si3N4 and whose cross section is L-shaped. In the manufacturing method, a pad film 2a, for stress relaxation, which is formed between the first oxidation-mask film pattern 3a and the semiconductor substrate 1 is formed of SiO2 by using a CVD method.

6. 发明专利

JPH09246130A SEMICONDUCTOR WAFER, MANUFACTURE THEREOF, AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH09246130A
公开(公告)日：1997-09-19
申请号：JP7839796
申请日：1996-03-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KANAI AKIRA , SHIMIZU HIROBUMI , SATO TOMOMI , SUZUKI NORIO
IPC分类号： H01L21/68 , H01L21/02 , H01L21/322 , H01S3/00 , H01S5/00 , H01S3/18
摘要： PROBLEM TO BE SOLVED: To provide a round wafer such that the position and crystallographic axis direction may be identified. SOLUTION: A manufacturing method of a round wafer 1 includes a longitudinal groove forming process for providing a longitudinal groove 12 in a predetermined crystal surface orientation of a block 11 ground in a columnar shape from a semiconductor ingot, a slicing process for cutting a thin plate 13 having a V-groove 14 from the block provided with the longitudinal groove, a singular property part forming process for forming a melting mark 18 having different property from other parts by irradiating the inner side of the V-groove of the thin plate with a laser 16, and a characteristic part forming process for removing the V-groove, then planarizing the main surface of the melting mark 18 and thus locally forming a characteristic part 5 having a flat surface and a different inner lattice strain 19 from the other parts, on a round semiconductor substrate 2. Thus, the round wafer may be aligned by detecting the characteristic part. With this round wafer, disorder in gas flow and thermal stress dislocation may be prevented at the time of IC manufacturing. Since the characteristic part has the inner property differing only locally, no deterioration in yield is generated.

7. 发明专利

JPH05121399A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05121399A
公开(公告)日：1993-05-18
申请号：JP23444791
申请日：1991-09-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , KOSAKA YUJI , ITO KATSUHIKO , SHIMIZU HIROBUMI , KAMIYAMA TAKAMITSU , WATANABE KEIICHI , TOKUNAGA KENJI , NAKAMURA ATSUSHI
IPC分类号： H01L21/76 , H01L21/316 , H01L27/08
摘要： PURPOSE:To suppress a bird's beak of an element isolation oxide film to be formed on a surface of a semiconductor substrate by implanting oxygen in the substrate with an Si nitride film as a mask, and heat treating the substrate with the nitride film as a mask for oxidation. CONSTITUTION:A semiconductor substrate 1 made of p type single-crystal silicon is heat-treated to form an oxide 2. After an Si nitride film 3 is deposited thereon, it is patterned. With the film 3 as a mask oxygen 4 is implanted in the substrate 1. With the film 3 as a mask for oxidation the substrate 1 is heat-treated, and an element isolation oxide film 5 is grown.

8. 发明专利

JPH10247731A SEMICONDUCTOR WAFER, AND MANUFACTURE THEREOF, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH10247731A
公开(公告)日：1998-09-14
申请号：JP5008797
申请日：1997-03-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SHIMIZU HIROBUMI , SUZUKI NORIO , SAITOU SHIGEAKI , MATSUDA YASUSHI , SUGINO YUSHI , TANAKA TOSHIHIDE
IPC分类号： C30B15/36 , C30B25/20 , C30B29/06 , C30B31/22 , C30B33/02 , H01L21/20 , H01L21/205 , H01L21/322 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/108 , H01L27/11 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a MIS(metal insulator semiconductor) device at a low cost, wherein the wafer is improved in gettering capacity and possessed of a gate oxide film (GOI) excellent in properties. SOLUTION: An epitaxial layer is made to grow on the main surface of a single crystal silicon wafer which is so tilted as to cross at right angles a crystal axis within an angle of 35 deg. from one of axes in the [010] direction in the (100) plane as a main plane and within an angle of 2.5 deg. to 15 deg. from a 100 crystal axis. By this setup, OSF(oxidation induced stacking fault) is restrained (a reduction in OSF dislocation density) from being induced on the surface (MISFET formation region) of the epitaxial layer, so that the silicon wafer of this constitution can be possessed of a heavy metal gettering capacity.

9. 发明专利

JPH10209170A SEMICONDUCTOR WAFER, ITS MANUFACTURE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ITS MANUFACTURE 失效
公开(公告)号：JPH10209170A
公开(公告)日：1998-08-07
申请号：JP700697
申请日：1997-01-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI NORIO , KIYOTA SHOGO , SHIMIZU HIROBUMI , SAITOU SHIGEAKI , SATO TOMOMI , MATSUDA YASUSHI , SUGINO YUSHI , TANAKA TOSHIHIDE , ISOMAE SEIICHI , TAKEDA KAZUO , ISHIHARA TETSUYA
IPC分类号： H01L21/8247 , H01L21/205 , H01L21/322 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/088 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide an epitaxial wafer for MIS devices at a low cost which has an improved gettering power and gate oxide film characteristics (GOI). SOLUTION: An epitaxial wafer having an epitaxial layer grown on a main surface of a single crystal Si wafer made by the Czochralski method has a microdefect density of 1×10 to 1×10 defects/cm as an epitaxially grown single crystal Si wafer. The epitaxial layer is 0.3-3μm thick, and contains an impurity boron of the same conductivity type less than 3×10 atoms/cm as that of the single crystal Si wafer 1.

10. 发明专利

JPH10189766A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION THEREOF, SEMICONDUCTOR WAFER AND FABRICATION THEREOF 失效
公开(公告)号：JPH10189766A
公开(公告)日：1998-07-21
申请号：JP22052697
申请日：1997-08-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUDA YASUSHI , SHIMIZU HIROBUMI , SUZUKI NORIO , KURODA KENICHI , SAITOU SHIGEAKI , SATO TOMOMI , TAKEDA KAZUO , KAWAMURA MASAO , SUGINO YUSHI
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce the fabrication cost of MIS device employing an epitaxial wafer. SOLUTION: Impurity ions are implanted with high energy into the vicinity of interface between an epitaxial layer 2 and a silicon substrate 1 to form an ion implantation layer 5. The ion implantation layer 5 serves as a barrier wall for prevent a latent flaw or a micro defect on the surface of the silicon substrate 1 from having a significant effect on the epitaxial layer 2. A structural defect in the ion implantation layer 5 caused through amorphous process serves as a gettering layer for capturing contaminants, e.g. heavy metals, intruding into the substrate in the way of the process. Furthermore, the heavily doped low resistance ion implantation layer 5 contributes to enhancement of latch-up resistance of a CMOSFET.

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