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1. 发明专利

JPH09298218A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09298218A
公开(公告)日：1997-11-18
申请号：JP11445296
申请日：1996-05-09
申请人： HITACHI LTD
发明人： TAKAHASHI HIROYUKI , ARAI TAKESHI , SUWA MOTOHIRO , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor device to deteriorate less in electric characteristics due to the reflection and radiation loss of signals by a method wherein a connecting part which connects a wiring layer to another wiring layer in a vertical direction is made tilted so as to make the vertical bent part of a transmission path obtuse. SOLUTION: A semiconductor chip 1 is hermetically sealed up in a laminated ceramic package 2, where the package 2 is composed of a board 3 where a multilayer interconnection is provided, a ceramic dam frame 4 provided in the periphery of the main surface of the board 3, and a cap 5 made of a gold- plated metal plate. The semiconductor chip 1 is hermetically sealed up in the package 2 in such a manner that the semiconductor chip 1 is bonded to the main surface of the board 3 through the intermediary of connectors 6 by being faced down, and after that, the cap 3 is fixed to the dam frame 4 to hermetically seal up the package. The connectors 6 are formed on pads 7 provided onto the main surface of the board 3 to transmit high-frequency signals, each composed of bump electrodes 6a and 6b which are made of gold or the like and laminated as staggered, and connected to the pads 7.

2. 发明专利

JPH0786328A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0786328A
公开(公告)日：1995-03-31
申请号：JP23040993
申请日：1993-09-16
申请人： HITACHI LTD
发明人： TAKAHASHI HIROYUKI , KAMATA CHIYOSHI , NAKAZATO NORIO
IPC分类号： H01L21/60
摘要： PURPOSE:To shorten the cycle time required for the wire bonding, to achieve a high-speed operation of a semiconductor integrated circuit device, and the reliability. CONSTITUTION:In a semiconductor integrated circuit device which has pellet 1 having an plurality of electrode pads 3 on the main face and whose electrode pad and inner lead 5 are electrically connected by a wire 6, an electrode pad 3 for signal is sandwiched with electrode pads 4 for earthing potential on the pellet. Moreover, in manufacturing, a plurality of wires 6 is simultaneously bonded with a bonding tool having a plurality of small holes, thereby realizing the purpose.

3. 发明专利

JPH0474433A METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0474433A
公开(公告)日：1992-03-09
申请号：JP18821090
申请日：1990-07-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI , MISHIMAGI HIROMITSU
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To remarkably enhance the connecting relaibility of an electrode to a bump electrode by a method wherein a metal foil is placed on the electrode on a mounting board, the electrode and the metal foil are heated and alloyed and the bump electrode is formed on the electrode. CONSTITUTION:An Au ribbon 11 is sucked and fixed onto a chuck block 35; a ribbon cutting blade 37 is lowered; the Au ribbon 11 is cut; an Au foil 12 having a prescribed area is formed. In succession, the foil is sucked by a chuck collet 39; it is conveyed to a metal-foil positioning part C; it is placed in the chip-mounting face of a package board 2. While the foil has been placed on a carrier 40, it is conveyed to a heating part D and is placed on a heating block 42. Then, in this state an electric current is applied to a heater 45 which has been built in the heating block 42; the package board 2 is heated to a prescribed temperature. Sn on the surface of electrodes 6 is diffused into the Au foil 12; a eutectic alloying reaction is caused; bump electrodes 7a which are composed of an Au-Sn alloy and which are in a molten state are formed on the respective electrodes 6 in a self-aligned manner. The residue of the Au foil 12 which has been sucked to a metal-foil fixation collet 43 is collected in a pocket 47; it is regenerated and utilized as the Au ribbon 11.

4. 发明专利

JPH01233744A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01233744A
公开(公告)日：1989-09-19
申请号：JP6162688
申请日：1988-03-14
申请人： HITACHI LTD
发明人： KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L23/02 , H01P5/08 , H05K9/00
摘要： PURPOSE:To enhance an isolation characteristic by a method wherein two or more constant-potential wiring parts are formed in the state of a coaxial cable around the signal wiring parts in the coaxial direction with reference to signal wiring parts and the signal wiring parts are shielded from each other to a degree identical to the coaxial cable. CONSTITUTION:A semiconductor chip 1 composed of GaAs or the like is mounted on the bottom of a cavity 101 in a substrate 100 via a metal film 2. The chip 1 is connected to electrodes 4 of the substrate 100 via bonding wires 3. An internal constant-potential wiring part 6 is formed between a signal wiring part 5 and a signal wiring part 5. External constant-potential wiring parts 7 are formed on side faces at the outside of the substrate 100. The signal wiring parts are shielded by the wiring parts 7, the wiring part 6 and the metal film 2. A cap 8 shields the bonding wires 3 and the chip 1 from an external electric field. By this setup, an isolation characteristic can be enhanced.

5. 发明专利

JPS63136533A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63136533A
公开(公告)日：1988-06-08
申请号：JP28172586
申请日：1986-11-28
申请人： HITACHI LTD
发明人： KUROKAWA ATSUSHI , MISHIMAGI HIROMITSU , KAMATA CHIYOSHI
IPC分类号： H01L21/52
摘要： PURPOSE:To mount a semiconductor pellet with a gold-tin alloy without varying the characteristics of a circuit element, etc., by applying and forming an intermediate layer consisting of one selected from at least titanium, chromium and molybdenum onto the semiconductor surface of the pellet. CONSTITUTION:A pellet 3 joined by a gold-tin alloy layer 4 is brought into contact with said gold-tin alloy layer 4 through an intermediate layer constituted of a first intermediate layer 9 applied onto the joint surface 3a of the pellet 3 and composed of titanium (Ti) and a second intermediate layer 10 applied to said first intermediate layer 9 and made up of nickel (Ni). To join the semiconductor pallet 3 to a package substrate 1, the semiconductor pallet 3 in which a gold layer 11 is applied onto the second intermediate layer 10 applied onto the first intermediate layer 9 on the joint surface 3a is prepared, and heated at a fixed temperature under the state in which foil 4A consisting of a gold-tin alloy is held between said gold layer 11 and the package substrate 1, and the pellet may be scrubbed.

6. 发明专利

JPS6342157A MULTI-CHIP MODULE 失效
公开(公告)号：JPS6342157A
公开(公告)日：1988-02-23
申请号：JP18507886
申请日：1986-08-08
申请人： HITACHI LTD
发明人： KAMATA CHIYOSHI
IPC分类号： H01L23/52
摘要： PURPOSE:To make it possible to implement matching of thermal expansion coefficients and reduce heat resistance, by bonding a mother chip to the rear surface of a metallic radiating fin, which serves the role of a base, and bonding element chips to the rear surface of a wiring substrate through salient electrodes. CONSTITUTION:A radiating fin 1 is formed as a unitary body with a base. A GaAs mother chip 2 is directly bonded to the flat plane of the rear surface (bottom surface) of a fin part 3. the radiating fin 1, which serves the role of the base, is formed of, e.g., metallic material whose thermal expansion coefficient is approximate to that of the GaAs mother chip 2. In the GaAs mother chip 2, circuit wiring is appropriately provided on a wafer composed of a GaAs compound semiconductor crystal. The circuit wiring, which is interconnected to each outer connecting terminal formed on a frame 6 with connecting wire 5, is guided outside of a multi-chip module. GaAs element chips 9 are bonded to the surface of the GaAs mother chip 2 through bumps 8. Thus matching of thermal expansion coefficients are obtained, and a heat radiating characteristics can be made excellent.

7. 发明专利

JPS62249457A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249457A
公开(公告)日：1987-10-30
申请号：JP9201186
申请日：1986-04-23
申请人： HITACHI LTD
发明人： KAMATA CHIYOSHI , HATTA YASUSHI
IPC分类号： H01L23/02 , H01L23/04 , H01L23/10
摘要： PURPOSE:To facilitate avoiding misoperation and so forth even if a semiconductor pellet which can process high speed calculation is mounted on a pellet mounting substrate by a method wherein a cap which seals the semiconductor pellet mounted on the pellet mounting substrate is made of conductive material and the cap is connected to a constant potential electrode. CONSTITUTION:A cap 8 made of conductive material is attached to the top surface of a substrate with conductive bonding agent 7 such as gold-tin soldering material between to seal the inside of a package. In the package substrate 1, through-hole wirings 9 and 9a which connect electrically a flat plate electrode 2 to a ground wiring layer 5 and the ground wiring layer 5 to the conductive bonding agent 7 respectively are vertically formed. Thus the flat plate electrode 2 and the cap 8 are electrically connected to the ground wiring layer 5 which is a constant potential electrode and are kept at the same potential as the ground wiring layer 5. With this constitution, even if a GaAs LSI 3 which can process signals with high speed is mounted, the reliability can be improved.

8. 发明专利

JPS6020522A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6020522A
公开(公告)日：1985-02-01
申请号：JP12763183
申请日：1983-07-15
申请人： HITACHI LTD
发明人： ISHIDA TAKASHI , SEKI MASATOSHI , SAWARA KUNIZOU , EMOTO YOSHIAKI , KAMATA CHIYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To obtain a wiring, dimensional accuracy thereof is high and resistance thereof is low, by forming the wiring on a package substrate by multilayer wiring consisting of titanium and copper. CONSTITUTION:A wiring 4 is formed as three layer thin-film multilayer wirings consisting of a titanium layer 10 formed on a package substrate 11 after sinterings through the evaporation of a thin-film, a copper layer 11 evaporated on the layer 10 in a thin-film shape and a titanium layer 12 evaporated on the layer 11 in the thin-film shape. A pedestal section 5 is composed of a copper layer 13 evaporated on the titanium layer 12 as the uppermost layer of the wiring 4 in the thin-film shape and a titanium layer 14 evaporated around the copper layer 13 in the thin-film shape. Since the wiring 4 is formed by the three layer thin- film evaporated layers of the titanium layer 10, the copper layer 11 and the titanium layer 12, the wiring 4 and the pedestal section 5 are formed with dimensional accuracy higher than a tungsten wiring formed through sintering. Accordingly, a large-sized pellet can be face-down bonded. The resistance of the wiring 4 can be lowered by the presence of the copper layer 11.

9. 发明专利

JPH06216272A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06216272A
公开(公告)日：1994-08-05
申请号：JP23215493
申请日：1993-09-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARADA TAKU , YOSHIHARA KAZUHIRO , MASUZAWA KAZUTAKA , HAYASHI TERUYOSHI , KUMAZAWA ATSUSHI , NAGAI KENJI , NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L23/13 , H01L23/498 , H01L23/66
摘要： PURPOSE:To realize matching of characteristic impedance of signal transmitting lines in a package for mounting a semiconductor chip on which ultra-high speed LSI is formed. CONSTITUTION:One end of a signal transmitting line 203 formed on the main surface of a package substrate 204 is extended up to the area just under a pad formed on the main surface of a semiconductor chip 201 and is then electrically connected to a pad on a semiconductor chip 201 via a bump electrode. Moreover, the other end of the signal transmitting line 203 is extended up to the external circumference of the main surface of the package substrate 204 and is then coupled with an external lead 205.

10. 发明专利

JPH04209558A SEMICONDUCTOR INTEGRATED CIRUCIT DEVICE 失效
公开(公告)号：JPH04209558A
公开(公告)日：1992-07-30
申请号：JP40047290
申请日：1990-12-05
申请人： HITACHI LTD
发明人： KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L25/00
摘要： PURPOSE:To stabilize an operation by disposing a power source plate provided in a cavity of an IC package in parallel with the main surface of a semiconductor chip, and connecting the plate to the chip via bonding wires extending in a direction perpendicular to the main surfaces. CONSTITUTION:A power source plate 12 is provided in parallel with a main surface of a semiconductor chip 7 in a gap between the chip 7 and a cap 4 in the cavity 6 of an IC package 1. A constant-potential plate 12a of the plate 12 and a reference potential plate 12b are insulated by an insulating layer 13, and connected to outer leads 11 and the chip 7 via through holes and bonding wires 14. The connection of the chip 7 via the wires 14 is conducted via an opening 15a, constant-potential, reference potential bonding pads are provided directly thereabove, and the wires 14 are extended in a direction perpendicular to the main surface of the chip 7 and the plate 12. Thus, stabilization of an IC in a microwave band and reduction in influences of a particle beam and an electromagnetic wave can be performed.

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