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1. 发明专利

JP2000294669A MANUFACTURE OF WIRING BOARD AND SEMICONDUCTOR DEVICE USING IT, AND THAT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000294669A
公开(公告)日：2000-10-20
申请号：JP9775499
申请日：1999-04-05
申请人： HITACHI LTD , NIPPON CMK KK
发明人： SUWA MOTOHIRO , MIWA TAKASHI , NOSE FUJIAKI , HARADA MEIKIYU
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To facilitate the handling without making package boards individual pieces, by providing a wiring board with a plurality of package boards which are equipped with slits at their peripheries, and providing one part of the slit with a coupling part which mechanically connects the package board with the periphery of the wiring board and is equipped with a recess at its one part. SOLUTION: A wiring board 1, which is equipped with a plurality of package boards 2, is provided with a slit 4 in the vicinity of each package board 2, and it is further provided with a coupling 5, which mechanically connects the package board 2 with the periphery 3 of the wiring board 1, at one part of the slit 4, and it is provided with a counterbore 6 at one part of the coupling 5. A plurality of package boards exist on that sheet, and the package boards 2 do not become individual pieces, so the handling of the board for the wiring board can be facilitated. Moreover, a sealing agent can be formed, making use of the counterbore 6 and the slit 4, when injecting the sealing agent for mounting electronic parts such as semiconductor chips, etc., mounted on the package board 2.

2. 发明专利

JP2000133742A PACKAGE SUBSTRATE, SEMICONDUCTOR DEVICE USING THE SAME, AND ITS MANUFACTURE 失效
公开(公告)号：JP2000133742A
公开(公告)日：2000-05-12
申请号：JP30239998
申请日：1998-10-23
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , MIWA TAKASHI , NOSE FUJIAKI
IPC分类号： H01L23/12 , H01L21/52
摘要： PROBLEM TO BE SOLVED: To prevent peeling of a semiconductor chip from a package substrate by improving the adhesive property between the chip and substrate. SOLUTION: An electrode 7 which gives a bias to the rear surface of a semiconductor chip is set up in the central part on the surface of the package base 2 of a package substrate 1. An annular opening 12 is made through an insulating film (first insulating film) 8 formed on the surface of the electrode 7. Then another insulating film (second insulating film) 9 is formed on the surface of the insulating film 8 in the annular openings 12.

3. 发明专利

JPH1056043A SEMICONDUCTOR DEVICE AND TAPE CARRIER USED FOR MANUFACTURE THEREOF 失效
公开(公告)号：JPH1056043A
公开(公告)日：1998-02-24
申请号：JP21120896
申请日：1996-08-09
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a TCP-type semiconductor device where outer leads are hardly separated from an insulating film and a tape carrier used for manufacturing the device. SOLUTION: A semiconductor device is equipped with a lead support 4 which is formed of insulating film and provided with a semiconductor chip mounting region 15, leads 3 which are formed on the main surface of the lead support 4 and possessed of one ends located in the semiconductor chip mounting region 15 and other ends extending outwards from the periphery of the lead support 4, an semiconductor chip 6 connected to the one end of the lead 3 through the intermediary of electrodes 7, and a sealer 2 which seals up the semiconductor chip 6, the one end of the lead 3, and at least a part of the lead support 4. In this case, a reinforcing layer 21 is formed on the rear side of the part of the lead 3 which protrudes from the peripheral edge of the lead support 4 extending up to the rear of the lead support 4.

4. 发明专利

JPH0831865A SEMICONDUCTOR DEVICE AND BALL BONDER 失效
公开(公告)号：JPH0831865A
公开(公告)日：1996-02-02
申请号：JP16923294
申请日：1994-07-21
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , TAKAHASHI HIROYUKI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To obtain a semiconductor device in which the size of bonding pad and bump is diversified while increasing the freedom in the arrangement. CONSTITUTION:Bumps 31, 32, 33, different in the size and the number of stages, are formed by ball bonding for a wiring board 2 and a semiconductor element 1 while arranging the height according to the variation in the number of stages. The semiconductor element 1 is face down bonded to the wiring board 2 through thermocompression thus obtaining a semiconductor device.

5. 发明专利

JPH0567686A SEMICONDUCTOR DEVICE WIRING 失效
公开(公告)号：JPH0567686A
公开(公告)日：1993-03-19
申请号：JP22783591
申请日：1991-09-09
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , SUWA MOTOHIRO , KUDO KAZUE
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PURPOSE:To provide a wiring structure where a Cu wiring layer is protected against etching damage when a through-hole is provided to an interlayer insulating film without deteriorating the lower Cu wiring layer in characteristics. CONSTITUTION:A Cu wiring is formed into a four-layered structure composed of an adhesive layer, a Cu wiring layer 6, a barrier layer 9, and an etching stopper layer 8, etching damage 16 induced when a through-hole is provided to the insulating film 9 is prevented from spreading beyond the etching stopper 8. By this setup, when a through-hole is provided to an interlayer insulating film on a wiring, the wiring can be protected against etching damage by an etching stopper layer.

6. 发明专利

JPH0529321A STRUCTURE AND MANUFACTURE OF SEMICONDUCTOR DEVICE WIRING 失效
公开(公告)号：JPH0529321A
公开(公告)日：1993-02-05
申请号：JP18432491
申请日：1991-07-24
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , SUWA MOTOHIRO , MIYAZAKI KUNIO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To effectively relax the concentration of an electric current on both ends of a disconnected part in a wiring layer and to restrain electromigration by a method wherein an wiring layer whose resistivity and film thickness are proper is introduced and the resistance between the wiring layer and a conductivity guarantee layer is adjusted. CONSTITUTION:A multilayer wiring has a structure wherein an intermediate layer 4 used to control an electric current is formed between an wiring layer 5 and a conductivity guarantee layer 3. Let the film thickness of the wiring layer 5 be t1(nm), its resistivity be sigma1(mu OMEGA cm), the film thickness of the conductivity guarantee layer 3 be t2(nm), its resistivity be sigma2(mu OMEGA cm), the film thickness of the intermediate layer 4 be t3(nm), its resistivity be sigma3(mu OMEGA cm). In this case, a material and the film thickness are combined so as to establish the following relationship: sigma1

7. 发明专利

JPH03105973A INTERCONNECTION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03105973A
公开(公告)日：1991-05-02
申请号：JP24222589
申请日：1989-09-20
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , SATO MITSUO , KAWABUCHI YASUSHI , SUWA MOTOHIRO , KOIZUMI MASAHIRO , ONUKI HITOSHI , MIYAZAKI KUNIO , TANIGAKI YUKIO
IPC分类号： H01L23/52 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L29/43
摘要： PURPOSE:To offer a laminated interconnection in which an interface between an interconnection layer and a barrier layer is stable against a heat treatment and whose reliability is high by a method wherein the barrier layer using a material which contains both a main-component element constituting said interconnection layer and a main-component element constituting a semiconductor element as main components is formed under the interconnection layer. CONSTITUTION:A barrier layer 3 is situated between an interconnection layer 4 and an Si semiconductor element 6, and acts as a barrier for a substance diffusion operation. The barrier layer is formed by a sputtering method using an alloy target of a ternary compound Mo(Al, Si)2 of Mo, Al and Si. In addition, an Al-1wt.% Si interconnection layer in 0.5mum is formed on its upper part by a sputtering method. In order to suppress a reaction between an Al alloy interconnection layer and the barrier layer Mo(Al, Si)2, a composition ratio of Al to Si in the barrier layer must be set in such a way that a ratio of Al is larger than that in Al:Si=0.2:1.8. As a metal element which can be used for the barrier layer, Ti, Zr, Hf, V, Nb, Ta, Cr, W or Re is available instead of Mo.

8. 发明专利

JP2003158238A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2003158238A
公开(公告)日：2003-05-30
申请号：JP2001354266
申请日：2001-11-20
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , KATAGIRI MITSUAKI , NAKAMURA ATSUSHI
IPC分类号： H01L25/18 , H01L25/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that can reduce crosstalk caused by induction even without many extra circuit elements arranged. SOLUTION: Parallel wiring portions 10A, 10B, and 1A in which the flowing direction of signals is inverted are formed at part of a signal route by turning the signal route in the course of the route without using any active circuit element, such as the inverter, etc., which inverts the phase of real signals. Since no inverter is interposed in the courses of the parallel wiring portions, the portions constitute parts of real wiring and do not require any extra circuit element. When signals are transmitted from one side of each parallel wiring portion, the signals are turned in the course is transmission and the transmitting direction of the signals is inverted. When the flowing direction of an electric current flowing through the parallel conductors is inverted, magnetic fields in different directions cancel each other due to electromagnetism and the occurrence of electromagnetic waves is suppressed. The parallel wiring portions 10A, 10B, and 1A can relieve and, in addition, can suppress the occurrence of crosstalk to nearby other wiring.

9. 发明专利

JP2003124383A SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：JP2003124383A
公开(公告)日：2003-04-25
申请号：JP2001320554
申请日：2001-10-18
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , MABUCHI YUICHI , NAKAMURA ATSUSHI , FUKUMOTO EIJI
IPC分类号： H01L23/12 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L27/04 , H01L31/0336
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is miniaturized by reducing the number of external power terminals while suppressing power noise, and an electronic device in which a bypass capacitor is efficiently packaged. SOLUTION: The device is provided with a package substrate in which a semiconductor chip having a plurality of output circuits and an electrode for supplying voltages to the output circuits is packaged on the front face, and an external terminal is provided on the rear face having a plurality of wiring layers. On the front face of the package substrate, the device is provided with a second electrode connecting one terminal to the electrode of the semiconductor chip, a first wiring means for commonly connecting respective second electrodes while including a wiring layer different from the wiring layer on the front face, a second wiring means for connecting a first electrode and correspondent one of external terminals provided on the rear face, and a plurality of third wiring means for connecting the first wiring means to a plurality of external terminals of a number summarized into a number less than that of second electrodes provided on the rear face.

10. 发明专利

JP2000077555A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2000077555A
公开(公告)日：2000-03-14
申请号：JP26088398
申请日：1998-08-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIRAISHI TOMOHIRO , MATSUNAGA TOSHIHIRO , SUWA MOTOHIRO , KUBOSONO MINORU , NOSE FUJIAKI , TSUTSUMI YASUKI , SHIRAI MASAYUKI , MIWA TAKASHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To ensure proper through-hole conductors and further reduce the pitch of the conductors.
SOLUTION: A BGA 2 of a BGA.IC 1 is provided with a base 3 as a core 4. A ground conductor 5 is formed on the first major surface of the core 4, and an insulating film 9 is formed on the entire ground conductor 5, a plurality of signal lines 10 being formed on the insulating film 9 into a radial pattern. A bonding pad 11 is formed on the inside ends of the signal lines 10, and a pad 12 for bump is connected electrically with the outside ends of the signal lines 10 through the through-hole conductors 15 formed into narrow through- holes 14. Since the pitch of the signal lines can be reduced by forming the through-holes into narrow shape, the wiring density of the signal lines can be improved. In addition, the diameter of the through-holes is small but their length is large and sufficient areas can be ensured on the inner surface of the through-holes. Therefore, the through-hole conductors can be formed properly, and degradation in the electrical characteristics of the through-hole conductors can be prevented.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：确保适当的通孔导体，进一步降低导体间距。解决方案：BGA.IC1的BGA2具有基体3作为芯4.在芯体4的第一主表面上形成接地导体5，并且在整个接地导体上形成绝缘膜9 如图5所示，多个信号线10在绝缘膜9上形成为径向图案。在信号线10的内侧形成有接合焊盘11，通过形成为窄通孔14的通孔导体15，将信号线10的外侧端部与凸起的焊盘12电连接。由于可以通过将通孔形成为窄的形状来减小信号线的间距，可以提高信号线的配线密度。此外，通孔的直径小，但是它们的长度大，并且在通孔的内表面上可以确保足够的面积。因此，可以适当地形成通孔导体，并且可以防止通孔导体的电特性的劣化。

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