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1. 发明授权

US06559004B1 Method for forming three dimensional semiconductor structure and three dimensional capacitor 有权
标题翻译：形成三维半导体结构和三维电容器的方法
公开(公告)号：US06559004B1
公开(公告)日：2003-05-06
申请号：US10011760
申请日：2001-12-11
申请人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
发明人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
IPC分类号： H01L21336
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
摘要翻译：一种用于形成具有垂直电容器而不是水平电容器的三维半导体结构的方法。该方法基本上至少包括在电介质层内形成底板的这些步骤，在底板上形成另一电介质层，在底板上移除所有电介质层，在底板上形成可选的衬垫和电容器电介质层，以及形成顶板电容电介质层。注意，底板的形状与底部连接和垂直手指相同，还注意到底板中的每个间隙都由电容器介电层和顶板填充。

2. 发明授权

US06583489B2 Method for forming interconnect structure with low dielectric constant 有权
公开(公告)号：US06583489B2
公开(公告)日：2003-06-24
申请号：US10103835
申请日：2002-03-25
申请人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
发明人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
IPC分类号： H01L2900
CPC分类号： H01L21/76802 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/318 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

3. 发明授权

US06806182B2 Method for eliminating via resistance shift in organic ILD 失效
标题翻译：消除有机ILD中电阻移位的方法
公开(公告)号：US06806182B2
公开(公告)日：2004-10-19
申请号：US10137274
申请日：2002-05-01
申请人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
发明人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
IPC分类号： H01L214763
CPC分类号： H01L21/02252 , H01L21/02118 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02304 , H01L21/02323 , H01L21/0234 , H01L21/3121 , H01L21/31695 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
摘要翻译：在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

4. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

5. 发明授权

US06617234B2 Method of forming metal fuse and bonding pad 失效
标题翻译：形成金属熔丝和焊盘的方法
公开(公告)号：US06617234B2
公开(公告)日：2003-09-09
申请号：US09835014
申请日：2001-04-13
申请人： Sung-Hsiung Wang , Yimin Huang , Chiung-Sheng Hsiung
发明人： Sung-Hsiung Wang , Yimin Huang , Chiung-Sheng Hsiung
IPC分类号： H01L2144
CPC分类号： H01L24/02 , H01L23/5256 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , Y10S438/978
摘要： A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.
摘要翻译：一种形成金属熔断器和焊盘的方法。在衬底中形成导电层。介电层形成在衬底上。电介质层具有露出导电层的一部分的开口。在电介质层上形成金属层。将金属层图案化以形成金属熔丝和接合焊盘。接合焊盘经由开口电连接到导电层。金属保险丝和接合垫都有底切的侧壁。垫片形成在金属保险丝和接合垫的底切侧壁上。最后，在衬底上形成暴露金属熔丝和焊盘的钝化层。

6. 发明申请

US20050001321A1 Interconnection structure and fabrication method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20050001321A1
公开(公告)日：2005-01-06
申请号：US10893632
申请日：2004-07-15
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
摘要翻译：互连结构及其制造方法。在衬底上依次形成第一有机低k材料层，应力再分配层，第二有机低k电介质层，随后在第一有机低k材料层中形成开口，应力再分布层，和第二有机低k电介质层。然后用导电材料填充开口以形成互连结构。应力再分配层的热膨胀系数接近于基板的热膨胀系数，而这种热膨胀系数与第一和第二有机低k材料层的热膨胀系数的差异更显着。

7. 发明授权

US07179732B2 Interconnection structure and fabrication method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07179732B2
公开(公告)日：2007-02-20
申请号：US10893632
申请日：2004-07-15
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
摘要翻译：互连结构及其制造方法。在衬底上依次形成第一有机低k材料层，应力再分配层，第二有机低k电介质层，随后在第一有机低k材料层中形成开口，应力再分布层，和第二有机低k电介质层。然后用导电材料填充开口以形成互连结构。应力再分配层的热膨胀系数接近于基板的热膨胀系数，而这种热膨胀系数与第一和第二有机低k材料层的热膨胀系数的差异更显着。

8. 发明申请

US20090004372A1 Electroless Niwp Adhesion and Capping Layers for Tft Copper Gate Process 审中-公开
标题翻译：用于Tft铜栅工艺的无电Niwp粘合层和封盖层
公开(公告)号：US20090004372A1
公开(公告)日：2009-01-01
申请号：US11995312
申请日：2005-07-13
申请人： Akinobu Nasu , Shyan-Fang Chen , Yi-Tsung Chen , Tsu-An Lin , Chiung-Sheng Hsiung
发明人： Akinobu Nasu , Shyan-Fang Chen , Yi-Tsung Chen , Tsu-An Lin , Chiung-Sheng Hsiung
IPC分类号： B05D5/12 , C09K19/52 , B32B17/06
CPC分类号： C23C18/50 , C23C18/1844 , C23C18/1893 , Y10T428/1095
摘要： Electroless NiWP layers are used for TFT Cu gate process. The NiWP deposition process comprises the following steps. (a) Cleaning of the base surface using for example UV light, ozone solution and/or alkaline mixture solution, (b) micro-etching of the base surface using, e.g. diluted acid, (c) catalyzation of the base surface using, e.g. SnCl 2 and PdCl 2 solutions, (d) conditioning of the base surface using reducing agent solution, and (e) NiWP deposition. It has been discovered that NiWP layers deposited under certain conditions could provide good adhesion to the glass substrate and to the Cu layer with a good Cu barrier capability. A NiWP layer in useful for adhesion, capping and/or barrier layers for TFT Cu gate process (e.g. for flat screen display panels).
摘要翻译：无电镀NiWP层用于TFT Cu栅极工艺。 NiWP沉积工艺包括以下步骤。（a）使用例如UV光，臭氧溶液和/或碱性混合物溶液清洗基底表面，（b）使用例如紫外光，稀释的酸，（c）基底表面的催化。 SnCl 2和PdCl 2溶液，（d）使用还原剂溶液调节基底表面，和（e）NiWP沉积。已经发现，在某些条件下沉积的NiWP层可以对玻璃基底和具有良好Cu阻挡能力的Cu层提供良好的粘附性。用于TFT Cu栅极工艺（例如用于平板显示面板）的粘合，封盖和/或阻挡层的NiWP层。

9. 发明授权

US06890851B2 Interconnection structure and fabrication method thereof 有权
公开(公告)号：US06890851B2
公开(公告)日：2005-05-10
申请号：US10449262
申请日：2003-05-29
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

10. 发明授权

US06174812B1 Copper damascene technology for ultra large scale integration circuits 有权
标题翻译：铜大马士革技术用于超大规模集成电路
公开(公告)号：US06174812B1
公开(公告)日：2001-01-16
申请号：US09328246
申请日：1999-06-08
申请人： Chiung-Sheng Hsiung , Wen-Yi Hsieh , Water Lur
发明人： Chiung-Sheng Hsiung , Wen-Yi Hsieh , Water Lur
IPC分类号： H01L2144
CPC分类号： H01L21/76873 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L21/76885 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly. The other deposition processes are subsequently performed the same way.
摘要翻译：公开了一种应用于超大规模集成（ULSI）电路制造的铜 - 钯合金镶嵌技术。首先，在氧化物层上或以金属间电介质（IMD）层方式沉积TaN势垒。然后将铜钯种子沉积在TaN屏障上。此外，将铜 - 钯间隙填充电镀层电镀在电介质氧化物层上。其次，进行铜 - 钯退火处理。然后通过化学机械抛光（CMP）工艺对铜 - 钯电镀表面进行平面化处理。第三，CoWP帽与平面化的铜 - 钯合金表面自对准。最后，第二IMD层沉积在第一IMD层上。此外，形成在所述CoWP覆盖层上的第二电介质层中的接触孔，然后直接将第一IMD层的CoWP帽与第二IMD层的铜 - 钯合金底面连接。随后以相同的方式进行其它沉积工艺。

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