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1. 发明授权

US06806182B2 Method for eliminating via resistance shift in organic ILD 失效
标题翻译：消除有机ILD中电阻移位的方法
公开(公告)号：US06806182B2
公开(公告)日：2004-10-19
申请号：US10137274
申请日：2002-05-01
申请人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
发明人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
IPC分类号： H01L214763
CPC分类号： H01L21/02252 , H01L21/02118 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02304 , H01L21/02323 , H01L21/0234 , H01L21/3121 , H01L21/31695 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
摘要翻译：在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

2. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

3. 发明授权

US06559004B1 Method for forming three dimensional semiconductor structure and three dimensional capacitor 有权
标题翻译：形成三维半导体结构和三维电容器的方法
公开(公告)号：US06559004B1
公开(公告)日：2003-05-06
申请号：US10011760
申请日：2001-12-11
申请人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
发明人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
IPC分类号： H01L21336
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
摘要翻译：一种用于形成具有垂直电容器而不是水平电容器的三维半导体结构的方法。该方法基本上至少包括在电介质层内形成底板的这些步骤，在底板上形成另一电介质层，在底板上移除所有电介质层，在底板上形成可选的衬垫和电容器电介质层，以及形成顶板电容电介质层。注意，底板的形状与底部连接和垂直手指相同，还注意到底板中的每个间隙都由电容器介电层和顶板填充。

4. 发明授权

US06583489B2 Method for forming interconnect structure with low dielectric constant 有权
公开(公告)号：US06583489B2
公开(公告)日：2003-06-24
申请号：US10103835
申请日：2002-03-25
申请人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
发明人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
IPC分类号： H01L2900
CPC分类号： H01L21/76802 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/318 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

5. 发明授权

US07834351B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07834351B2
公开(公告)日：2010-11-16
申请号：US12426995
申请日：2009-04-21
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hsueh-Chung Chen
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hsueh-Chung Chen
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.
摘要翻译：公开了一种半导体器件。该器件包括衬底和覆盖衬底的第一布线层。第一布线层包括由第一密封环包围的第一布线区域。第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。第一监视器电路响应于在第三电介质层中发生预定量的变形。

6. 发明授权

US07651893B2 Metal electrical fuse structure 有权
标题翻译：金属电熔丝结构
公开(公告)号：US07651893B2
公开(公告)日：2010-01-26
申请号：US11320233
申请日：2005-12-27
申请人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.
摘要翻译：提供电熔丝及其形成方法。电熔丝包括在浅沟槽隔离区域上的电介质层和从电介质层的顶表面延伸到浅沟槽隔离区域的接触插塞，其中接触插塞包括基本上比两个端部部分窄的中间部分。接触插头形成熔丝元件。电熔丝还包括在电介质层上的金属化层中的两条金属线，其中两条金属线中的每一条连接到接触插塞的不同端部。

7. 发明申请

US20070145515A1 Metal electrical fuse structure 有权
标题翻译：金属电熔丝结构
公开(公告)号：US20070145515A1
公开(公告)日：2007-06-28
申请号：US11320233
申请日：2005-12-27
申请人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.
摘要翻译：提供电熔丝及其形成方法。电熔丝包括在浅沟槽隔离区域上的电介质层和从电介质层的顶表面延伸到浅沟槽隔离区域的接触插塞，其中接触插塞包括基本上比两个端部部分窄的中间部分。接触插头形成熔丝元件。电熔丝还包括在电介质层上的金属化层中的两条金属线，其中两条金属线中的每一条连接到接触插塞的不同端部。

8. 发明申请

US20050085069A1 Dual damascene partial gap fill polymer fabrication process 失效
标题翻译：双镶嵌部分间隙填充聚合物制造工艺
公开(公告)号：US20050085069A1
公开(公告)日：2005-04-21
申请号：US09863647
申请日：2001-05-23
申请人： Chingfu Lin , Hsueh-Chung Chen
发明人： Chingfu Lin , Hsueh-Chung Chen
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808
摘要： A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.
摘要翻译：提供具有导电层的基板。然后在导电层上方形成电介质层。然后在电介质层中形成至少一个通孔，以暴露导电层的一部分。然后用间隙填充聚合物层覆盖导电层，以完全填充通孔。执行化学机械抛光步骤以去除通孔外部的部分间隙填充聚合物层。执行蚀刻步骤以去除残留在通孔中的部分间隙填充聚合物层的一部分，导致部分间隙填充聚合物。进行光刻工艺以在电介质层上形成图案化的光致抗蚀剂层。光致抗蚀剂层具有露出通孔和部分间隙填充聚合物的开口。通过开口暴露的电介质层的一部分被蚀刻掉，以在电介质层中形成沟槽。然后去除光致抗蚀剂层和部分填充聚合物层，以暴露导电层的一部分。通孔和沟槽用金属材料填充，同时形成插头和线。

9. 发明授权

US06580508B1 Method for monitoring a semiconductor wafer in a chemical mechanical polishing process 有权
标题翻译：在化学机械抛光工艺中监测半导体晶片的方法
公开(公告)号：US06580508B1
公开(公告)日：2003-06-17
申请号：US09449533
申请日：1999-11-29
申请人： Hsueh-Chung Chen , Chien-Hung Chen , Juan-Yuan Wu
发明人： Hsueh-Chung Chen , Chien-Hung Chen , Juan-Yuan Wu
IPC分类号： G01N2155
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12
摘要： The present invention provides a monitoring method for monitoring a semiconductor wafer, in a chemical mechanical polishing (CMP) process. The CMP process is used to polish a dielectric layer of the semiconductor. The monitoring method comprises: 1. exposing the dielectric layer of the semiconductor wafer to an input light beam of fixed wavelength at a predetermined angle to generate a reflected light beam within a predetermined time period after performing the CMP process, the intensity of the reflected light beam undergoing periodic changes in response to the gradual thinning of the dielectric layer during the CMP process, 2. monitoring the intensity of the reflected light beam at a starting period within the predetermined time period and obtaining a periodic change rule according to the periodic changes of the intensity of the reflected light beam, and 3. monitoring the intensity of the reflected light beam throughout the rest of the predetermined time period and generating an output signal to stop the CMP process if the change of the intensity of the reflected light beam is not in accordance with the periodic change rule.
摘要翻译：本发明提供了一种用于在化学机械抛光（CMP）工艺中监测半导体晶片的监控方法。 CMP工艺用于抛光半导体的电介质层。监视方法包括：1.将半导体晶片的电介质层以预定角度曝光到固定波长的输入光束，以在执行CMP处理之后的预定时间段内产生反射光束，反射光的强度在CMP工艺期间响应于电介质层逐渐变薄的光束经历周期性变化，2.在预定时间段内在起始时段监测反射光束的强度，并根据周期性变化规律获得周期性变化规律反射光束的强度，以及3.在预定时间段的其余时间内监测反射光束的强度，并且如果反射光束的强度的变化不是，则产生输出信号以停止CMP处理按照定期变更规则。

10. 发明授权

US06544373B2 Polishing pad for a chemical mechanical polishing process 有权
标题翻译：抛光垫用于化学机械抛光工艺
公开(公告)号：US06544373B2
公开(公告)日：2003-04-08
申请号：US09682137
申请日：2001-07-26
申请人： Hsueh-Chung Chen , Teng-Chun Tsai
发明人： Hsueh-Chung Chen , Teng-Chun Tsai
IPC分类号： B32B3100
CPC分类号： B24B37/26 , B24B37/24 , Y10T156/1056 , Y10T156/1064 , Y10T156/1074 , Y10T156/1082
摘要： The present invention gives a method of fabricating a composite polishing pad. A first polishing pad has a glue layer on a surface of the first polishing pad and a number of hard polishing materials positioned on the glue layer. Then portions of the first polishing pad are punched off to remove portions of the hard polishing material positioned on the surface of the first polishing pad so as to form holes penetrating the first polishing pad. A second polishing pad has a glue layer on a surface of the second polishing pad, and soft polishing materials adhere to the glue layer. Then portions of the soft polishing material positioned on the surface of the second polishing pad are removed while retaining the glue layer, and the portions of the soft polishing material retained on the surface of the second polishing pad completely match the holes formed in the first polishing pad. Finally, the first polishing pad is stuck on the surface of the second polishing pad so as to form a composite polishing pad having a pattern formed by the hard and soft polishing materials on the surface of the composite polishing pad.
摘要翻译：本发明提供一种制造复合抛光垫的方法。第一抛光垫在第一抛光垫的表面上具有胶层和位于胶层上的多个硬抛光材料。然后将第一抛光垫的一部分冲压掉以去除位于第一抛光垫表面上的硬抛光材料的部分，从而形成贯穿第一抛光垫的孔。第二抛光垫在第二抛光垫的表面上具有胶层，并且软抛光材料粘附到胶层上。然后，在保持胶层的同时去除位于第二抛光垫的表面上的软抛光材料的部分，并且保留在第二抛光垫表面上的软抛光材料部分与第一抛光中形成的孔完全匹配垫。最后，将第一抛光垫粘贴在第二抛光垫的表面上，以便形成复合抛光垫，该复合抛光垫具有由复合抛光垫表面上的硬和软抛光材料形成的图案。

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