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1. 发明授权

US08987085B2 Methods for improving uniformity of cap layers 有权
标题翻译：改善盖层均匀性的方法
公开(公告)号：US08987085B2
公开(公告)日：2015-03-24
申请号：US11524000
申请日：2006-09-20
申请人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译：形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

2. 发明授权

US08432040B2 Interconnection structure design for low RC delay and leakage 有权
标题翻译：低RC延迟和泄漏的互连结构设计
公开(公告)号：US08432040B2
公开(公告)日：2013-04-30
申请号：US11444629
申请日：2006-06-01
申请人： Chen-Hua Yu , Ming-Shih Yeh
发明人： Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L29/41
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.
摘要翻译：提供了具有减小的RC延迟和泄漏的集成电路的互连结构。互连结构包括第一电介质层中的第一导电线，第一电介质层和第一导电线上的第二电介质层，以及第二电介质层中的双镶嵌结构。双镶嵌结构包括第二导电线和在第一和第二导电线之间和之间相邻的通孔，其中第二导电线包括直接在通孔上并邻接通孔的第一部分，以及不具有下面和相邻通孔的第二部分。第二部分具有小于第一部分的第一宽度的第二宽度。

3. 发明授权

US08109407B2 Apparatus for storing substrates 有权
标题翻译：用于存储基板的装置
公开(公告)号：US08109407B2
公开(公告)日：2012-02-07
申请号：US11755508
申请日：2007-05-30
申请人： Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Jui-Pin Hung , Ming-Shih Yeh
发明人： Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Jui-Pin Hung , Ming-Shih Yeh
IPC分类号： B65D45/28 , B65D53/06
CPC分类号： H01L21/67373 , H01L21/67376 , H01L21/67389
摘要： An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second member with a second arm extends from a second rib of the second member. The first and second arms are connected to the rotational apparatus. At least one corner member has a first edge. The first edge has a shape corresponding to a shape of a corner of the frame. The corner member is connected to a first end of the third arm. A second end of the third arm is connected to the rotational apparatus. A sealing material is disposed along a first longitudinal side of the first rib and a second longitudinal side of the second rib.
摘要翻译：一种装置包括外壳和构造成密封外壳的门。门包括一个板。旋转装置设置在板上。具有第一臂的至少一个第一构件从第一构件的第一肋延伸。具有第二臂的至少一个第二构件从第二构件的第二肋延伸。第一和第二臂连接到旋转装置。至少一个角部件具有第一边缘。第一边缘具有与框架的角部的形状对应的形状。角部件连接到第三臂的第一端。第三臂的第二端连接到旋转装置。密封材料沿着第一肋的第一纵向侧面和第二肋的第二纵向侧面设置。

4. 发明授权

US07651943B2 Forming diffusion barriers by annealing copper alloy layers 有权
标题翻译：通过退火铜合金层形成扩散阻挡层
公开(公告)号：US07651943B2
公开(公告)日：2010-01-26
申请号：US12032968
申请日：2008-02-18
申请人： Chen-Hua Yu , Ming Han Lee , Ming-Shih Yeh
发明人： Chen-Hua Yu , Ming Han Lee , Ming-Shih Yeh
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.
摘要翻译：形成集成电路的互连结构的方法包括提供半导体衬底; 在所述半导体衬底上形成介电层; 在介电层中形成开口; 并在开口中形成铜合金种子层。铜合金种子层物理接触介电层。铜合金种子层包括铜和合金材料。该方法还包括将金属材料填充在铜合金种子层的开口中和上方; 执行平坦化以在电介质层上除去多余的金属材料; 并进行热退火以使铜合金种子层中的合金材料与铜分离。

5. 发明申请

US20090209099A1 Forming Diffusion Barriers by Annealing Copper Alloy Layers 有权
标题翻译：通过退火铜合金层形成扩散壁垒
公开(公告)号：US20090209099A1
公开(公告)日：2009-08-20
申请号：US12032968
申请日：2008-02-18
申请人： Chen-Hua Yu , Ming Han Lee , Ming-Shih Yeh
发明人： Chen-Hua Yu , Ming Han Lee , Ming-Shih Yeh
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.
摘要翻译：形成集成电路的互连结构的方法包括提供半导体衬底; 在所述半导体衬底上形成介电层; 在介电层中形成开口; 并在开口中形成铜合金种子层。铜合金种子层物理接触介电层。铜合金种子层包括铜和合金材料。该方法还包括将金属材料填充在铜合金种子层的开口中和上方; 执行平坦化以在电介质层上除去多余的金属材料; 并进行热退火以使铜合金种子层中的合金材料与铜分离。

6. 发明申请

US20070278681A1 Interconnection structure design for low RC delay and leakage 有权
标题翻译：低RC延迟和泄漏的互连结构设计
公开(公告)号：US20070278681A1
公开(公告)日：2007-12-06
申请号：US11444629
申请日：2006-06-01
申请人： Chen-Hua Yu , Ming-Shih Yeh
发明人： Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L23/52
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.
摘要翻译：提供了具有减小的RC延迟和泄漏的集成电路的互连结构。互连结构包括第一电介质层中的第一导电线，第一电介质层和第一导电线上的第二电介质层，以及第二电介质层中的双镶嵌结构。双镶嵌结构包括第二导电线和在第一和第二导电线之间和之间相邻的通孔，其中第二导电线包括直接在通孔上并邻接通孔的第一部分，以及不具有下面和相邻通孔的第二部分。第二部分具有小于第一部分的第一宽度的第二宽度。

7. 发明申请

US20050001321A1 Interconnection structure and fabrication method thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20050001321A1
公开(公告)日：2005-01-06
申请号：US10893632
申请日：2004-07-15
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.
摘要翻译：互连结构及其制造方法。在衬底上依次形成第一有机低k材料层，应力再分配层，第二有机低k电介质层，随后在第一有机低k材料层中形成开口，应力再分布层，和第二有机低k电介质层。然后用导电材料填充开口以形成互连结构。应力再分配层的热膨胀系数接近于基板的热膨胀系数，而这种热膨胀系数与第一和第二有机低k材料层的热膨胀系数的差异更显着。

8. 发明申请

US20120190191A1 Process for Improving Copper Line Cap Formation 有权
标题翻译：改善铜线帽形成的工艺
公开(公告)号：US20120190191A1
公开(公告)日：2012-07-26
申请号：US13440704
申请日：2012-04-05
申请人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
发明人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76865 , H01L21/76883
摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.
摘要翻译：集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在导线。

9. 发明授权

US08106512B2 Low resistance high reliability contact via and metal line structure for semiconductor device 有权
标题翻译：低电阻高可靠性接触通孔和半导体器件的金属线结构
公开(公告)号：US08106512B2
公开(公告)日：2012-01-31
申请号：US12845852
申请日：2010-07-29
申请人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
发明人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/28562 , H01L21/76846 , H01L21/76867 , H01L21/76873 , H01L21/76883 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.
摘要翻译：上述结构和方法提供了提高互连可靠性和电阻率的机制。通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

10. 发明授权

US06890851B2 Interconnection structure and fabrication method thereof 有权
公开(公告)号：US06890851B2
公开(公告)日：2005-05-10
申请号：US10449262
申请日：2003-05-29
申请人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
发明人： Chiung-Sheng Hsiung , Chih-Chao Yang , Gwo-Shil Yang , Ming-Shih Yeh , Jen-Kon Chen
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807
摘要： An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

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