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1. 发明申请

US20060067225A1 Hierarchical flow control for router ATM interfaces 有权
公开(公告)号：US20060067225A1
公开(公告)日：2006-03-30
申请号：US10949916
申请日：2004-09-24
申请人： Guy Fedorkow , Kenneth Potter , Mark Gustlin , Christopher Kappler , Robert Olsen
发明人： Guy Fedorkow , Kenneth Potter , Mark Gustlin , Christopher Kappler , Robert Olsen
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L12/5601 , H04L47/266 , H04L2012/562 , H04L2012/5679 , H04L2012/5681
摘要： Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.

2. 发明申请

US20060277346A1 Port adapter for high-bandwidth bus 有权
标题翻译：用于高带宽总线的端口适配器
公开(公告)号：US20060277346A1
公开(公告)日：2006-12-07
申请号：US11502965
申请日：2006-08-11
申请人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , John Prokopik , Mohammed Tatar , Michael Taylor
发明人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , John Prokopik , Mohammed Tatar , Michael Taylor
IPC分类号： G06F13/14
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.
摘要翻译：公开了一种用于将零个或多个网络接口连接到具有SPI-4总线的主机系统的端口适配器。端口适配器包括零个或多个网络接口; 耦合到主机系统的SPI-4总线以在主机和网络接口之间提供通信信道; 耦合到所述主机系统的用于控制和监视所述端口适配器的控制总线; 以及将SPI-4总线和控制总线连接到网络接口的接口逻辑。提供了用于选择和使用用于各种联网技术的小的多种不同分组格式之一的方法，使得端口适配器可以隐藏其从主机系统处理的技术的细节，并且用于操作主机系统的SPI-4总线基于端口适配器的带宽要求，以几种速度之一。

3. 发明申请

US20070283073A1 Port adapter for high-bandwidth bus 有权
标题翻译：用于高带宽总线的端口适配器
公开(公告)号：US20070283073A1
公开(公告)日：2007-12-06
申请号：US11818006
申请日：2007-06-12
申请人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , Mohammed Tatar
发明人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , Mohammed Tatar
IPC分类号： G06F13/14
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.
摘要翻译：公开了一种用于将零个或多个网络接口连接到具有SPI-4总线的主机系统的端口适配器。端口适配器包括零个或多个网络接口; 耦合到主机系统的SPI-4总线以在主机和网络接口之间提供通信信道; 耦合到所述主机系统的用于控制和监视所述端口适配器的控制总线; 以及将SPI-4总线和控制总线连接到网络接口的接口逻辑。提供了用于选择和使用用于各种联网技术的小的多种不同分组格式之一的方法，使得端口适配器可以隐藏其从主机系统处理的技术的细节，以及用于操作主机系统的SPI-4总线基于端口适配器的带宽要求，以几种速度之一。

4. 发明申请

US20050149651A1 Port adapter for high-bandwidth bus 有权
标题翻译：用于高带宽总线的端口适配器
公开(公告)号：US20050149651A1
公开(公告)日：2005-07-07
申请号：US10680842
申请日：2003-10-06
申请人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , John Prokopik , Mohammed Tatar , Michael Taylor
发明人： David Doak , Garry Epps , Guy Fedorkow , Mark Gustlin , Steven Holmes , Randall Johnson , Promode Nedungadi , John Prokopik , Mohammed Tatar , Michael Taylor
IPC分类号： G06F3/00 , G06F13/38 , G06F13/40 , H04L12/28
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.
摘要翻译：公开了一种用于将零个或多个网络接口连接到具有SPI-4总线的主机系统的端口适配器。端口适配器包括零个或多个网络接口; 耦合到主机系统的SPI-4总线以在主机和网络接口之间提供通信信道; 耦合到所述主机系统的用于控制和监视所述端口适配器的控制总线; 以及将SPI-4总线和控制总线连接到网络接口的接口逻辑。提供了用于选择和使用用于各种联网技术的小的多种不同分组格式之一的方法，使得端口适配器可以隐藏其从主机系统处理的技术的细节，并且用于操作主机系统的SPI-4总线基于端口适配器的带宽要求，以几种速度之一。

5. 发明授权

US07693985B2 Technique for dispatching data packets to service control engines 有权
标题翻译：将数据包发送到服务控制引擎的技术
公开(公告)号：US07693985B2
公开(公告)日：2010-04-06
申请号：US11450929
申请日：2006-06-09
申请人： Michael Keohane , Guy Fedorkow , Gaash Hazan , Ori Finkelman , Ofer Weill
发明人： Michael Keohane , Guy Fedorkow , Gaash Hazan , Ori Finkelman , Ofer Weill
IPC分类号： G06F15/173 , G06F15/16 , H04L12/28
CPC分类号： H04L12/4641
摘要： A dispatching technique dispatches packets to a plurality of service control engines (SCEs) which in aggregate may be configured to handle traffic produced by a high-speed high-capacity data link. Upstream and downstream packets that are associated with a data flow between a subscriber and a destination node in a communication network are received from by a dispatcher which is located in a path used by the data flow. For each packet, the dispatcher identifies an SCE from among a plurality of SCEs that is to receive the packet based upon an address contained in the packet. The packet is then dispatched by the dispatcher to the identified SCE which processes the packet accordingly. After processing the packet, the SCE returns the packet to the dispatcher which further processes the packet including transferring the packet onto the communication network towards its destination.
摘要翻译：分派技术将分组分派到多个服务控制引擎（SCE），这些服务控制引擎可以被配置为处理由高速大容量数据链路产生的流量。与通信网络中的订户和目的地节点之间的数据流相关联的上游和下游分组由位于数据流所使用的路径中的调度器接收。对于每个分组，分派器根据包中包含的地址从要接收分组的多个SCE中识别SCE。然后，分组由分派器发送到相应处理分组的所识别的SCE。在处理分组之后，SCE将分组返回给调度器，分派器进一步处理分组，包括将分组传送到通信网络上的目的地。

6. 发明申请

US20070288615A1 Technique for dispatching data packets to service control engines 有权
标题翻译：将数据包发送到服务控制引擎的技术
公开(公告)号：US20070288615A1
公开(公告)日：2007-12-13
申请号：US11450929
申请日：2006-06-09
申请人： Michael Keohane , Guy Fedorkow , Gaash Hazan , Ori Finkelman , Ofer Weill
发明人： Michael Keohane , Guy Fedorkow , Gaash Hazan , Ori Finkelman , Ofer Weill
IPC分类号： G06F15/173
CPC分类号： H04L12/4641
摘要： A dispatching technique dispatches packets to a plurality of service control engines (SCEs) which in aggregate may be configured to handle traffic produced by a high-speed high-capacity data link. Upstream and downstream packets that are associated with a data flow between a subscriber and a destination node in a communication network are received from by a dispatcher which is located in a path used by the data flow. For each packet, the dispatcher identifies an SCE from among a plurality of SCEs that is to receive the packet based upon an address contained in the packet. The packet is then dispatched by the dispatcher to the identified SCE which processes the packet accordingly. After processing the packet, the SCE returns the packet to the dispatcher which further processes the packet including transferring the packet onto the communication network towards its destination.
摘要翻译：分派技术将分组分派到多个服务控制引擎（SCE），这些服务控制引擎可以被配置为处理由高速大容量数据链路产生的流量。与通信网络中的订户和目的地节点之间的数据流相关联的上游和下游分组由位于数据流所使用的路径中的调度器接收。对于每个分组，分派器根据包中包含的地址从要接收分组的多个SCE中识别SCE。然后，分组由分派器发送到相应处理分组的所识别的SCE。在处理分组之后，SCE将分组返回给调度器，分派器进一步处理分组，包括将分组传送到通信网络上的目的地。

7. 发明授权

US5896427A System and method for maintaining network synchronization utilizing digital phase comparison techniques with synchronous residual time stamps 失效
标题翻译：利用具有同步残留时间戳的数字相位比较技术来维护网络同步的系统和方法
公开(公告)号：US5896427A
公开(公告)日：1999-04-20
申请号：US127576
申请日：1998-07-31
申请人： Gary S. Muntz , Steven E. Jacobs , Guy Fedorkow
发明人： Gary S. Muntz , Steven E. Jacobs , Guy Fedorkow
IPC分类号： H04J3/06 , H04L12/56 , H04Q11/04 , H04L25/36 , H04L7/00 , H04L25/40
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5674
摘要： A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value. The clock generation stage adjusts the transmit clock in response to a filtered control value and transmits the source data to the destination CPE at the adjusted transmit clock frequency. By maintaining a constant phase offset, the frequencies of the receive clock of the source node and the transmit clock of the destination node are synchronized, thereby providing CBR service. In addition to performing SRTS clock recovery techniques, the destination module may also be configured to perform adaptive clock recovery (ACR) and synchronous network clock (SNC) techniques.
摘要翻译：一种网络节点目的地模块，用于确保通过具有包括用于接收信息的输入级的可选网络参考时钟的网络的适当接收和传输信息;同步残余时间戳（SRTS）定时控制级，用于实现数字相位比较技术，网络参考时钟和用于响应于由SRTS定时控制级产生的控制值产生发送时钟的时钟生成级。 SRTS定时控制级在源节点的接收时钟与目的节点的发送时钟之间维持恒定的相位偏移。 SRTS定时控制级包括RTS采样发生器，用于产生用于与源RTS采样进行比较的本地RTS采样，以确定源和时钟之间的当前相位偏移。然后将当前相位偏移与存储在相位寄存器中的目标相位偏移进行比较以产生控制值。时钟发生级响应于滤波的控制值来调整发送时钟，并以调整的发送时钟频率将源数据发送到目的地CPE。通过保持恒定的相位偏移，源节点的接收时钟的频率和目的地节点的发送时钟被同步，从而提供CBR服务。除了执行SRTS时钟恢复技术之外，目的地模块还可以被配置为执行自适应时钟恢复（ACR）和同步网络时钟（SNC）技术。

8. 发明授权

US07111102B2 Port adapter for high-bandwidth bus 有权
公开(公告)号：US07111102B2
公开(公告)日：2006-09-19
申请号：US10680842
申请日：2003-10-06
申请人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
发明人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
IPC分类号： G06F13/14 , H04L9/00
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

9. 发明授权

US5822383A System and method for maintaining network synchronization utilizing digital phase comparison techniques with synchronous residual time stamps 失效
公开(公告)号：US5822383A
公开(公告)日：1998-10-13
申请号：US573197
申请日：1995-12-15
申请人： Gary S. Muntz , Steven E. Jacobs , Guy Fedorkow
发明人： Gary S. Muntz , Steven E. Jacobs , Guy Fedorkow
IPC分类号： H04J3/06 , H04L12/56 , H04Q11/04 , H04L7/04
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5674
摘要： A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value. The clock generation stage adjusts the transmit clock in response to a filtered control value and transmits the source data to the destination CPE at the adjusted transmit clock frequency. By maintaining a constant phase offset, the frequencies of the receive clock of the source node and the transmit clock of the destination node are synchronized, thereby providing CBR service. In addition to performing SRTS clock recovery techniques, the destination module may also be configured to perform adaptive clock recovery (ACR) and synchronous network clock (SNC) techniques.

10. 发明授权

US07433988B2 Port adapter for high-bandwidth bus 有权
标题翻译：用于高带宽总线的端口适配器
公开(公告)号：US07433988B2
公开(公告)日：2008-10-07
申请号：US11818006
申请日：2007-06-12
申请人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , Mohammed I. Tatar
发明人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , Mohammed I. Tatar
IPC分类号： G06F13/14 , H04B7/00 , H04L12/66
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.
摘要翻译：公开了一种用于将零个或多个网络接口连接到具有SPI-4总线的主机系统的端口适配器。端口适配器包括零个或多个网络接口; 耦合到主机系统的SPI-4总线以在主机和网络接口之间提供通信信道; 耦合到所述主机系统的用于控制和监视所述端口适配器的控制总线; 以及将SPI-4总线和控制总线连接到网络接口的接口逻辑。提供了用于选择和使用用于各种联网技术的小的多种不同分组格式之一的方法，使得端口适配器可以隐藏其从主机系统处理的技术的细节，并且用于操作主机系统的SPI-4总线基于端口适配器的带宽要求，以几种速度之一。

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