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1. 发明授权

US07729351B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07729351B2
公开(公告)日：2010-06-01
申请号：US11365017
申请日：2006-03-01
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets. These features can include a recycle path coupling a gather stage circuit and a fetch stage circuit and can include sequence number logic configured to associate sequence numbers with multicast packet headers.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。这些特征可以包括耦合收集阶段电路和获取级电路的再循环路径，并且可以包括被配置为将序列号与多播分组报头相关联的序列号逻辑。

2. 发明授权

US07809009B2 Pipelined packet switching and queuing architecture 有权
公开(公告)号：US07809009B2
公开(公告)日：2010-10-05
申请号：US11358860
申请日：2006-02-21
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04J1/16 , H04L12/56
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.

3. 发明授权

US07408878B2 System packet interface 有权
标题翻译：系统分组接口
公开(公告)号：US07408878B2
公开(公告)日：2008-08-05
申请号：US10458357
申请日：2003-06-10
申请人： Adrian B. Evans , Mohammed I. Tatar , Cedrik K. Begin
发明人： Adrian B. Evans , Mohammed I. Tatar , Cedrik K. Begin
IPC分类号： H04L12/26
CPC分类号： H04L49/30
摘要： An apparatus including a first integrated circuit (IC), a second IC, and an interface coupling the first IC to the second IC. The interface transfers payload control information between the first IC and the second IC utilizing a number of data transmission lines. On the clock cycle transition following the transfer of payload control information, the interface transfers packetized data between the first IC and the second IC at a data rate of at least approximately 20 Gbps utilizing the same transmission lines. A one-bit control signal is used by the interface to identify when payload control information is present on all of the data transmission lines.
摘要翻译：一种包括第一集成电路（IC），第二IC以及将第一IC耦合到第二IC的接口的装置。接口使用多条数据传输线路在第一IC和第二IC之间传输有效载荷控制信息。在传送有效负载控制信息之后的时钟周期转换中，接口使用相同的传输线以至少约20Gbps的数据速率在第一IC和第二IC之间传送分组数据。接口使用一位控制信号来识别何时有效载荷控制信息存在于所有数据传输线上。

4. 发明授权

US07310695B2 Port adapter for high-bandwidth bus 有权
公开(公告)号：US07310695B2
公开(公告)日：2007-12-18
申请号：US11502965
申请日：2006-08-11
申请人： Garry P. Epps , Mark A. Gustlin , Mohammed I. Tatar
发明人： Garry P. Epps , Mark A. Gustlin , Mohammed I. Tatar
IPC分类号： G06F13/14 , H04B7/00 , H04L12/66
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

5. 发明授权

US07111102B2 Port adapter for high-bandwidth bus 有权
公开(公告)号：US07111102B2
公开(公告)日：2006-09-19
申请号：US10680842
申请日：2003-10-06
申请人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
发明人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
IPC分类号： G06F13/14 , H04L9/00
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

6. 发明申请

US20110064084A1 PIPELINED PACKET SWITCHING AND QUEUING ARCHITECTURE 有权
标题翻译：管道分配开关和排队建筑
公开(公告)号：US20110064084A1
公开(公告)日：2011-03-17
申请号：US12952601
申请日：2010-11-23
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

7. 发明授权

US07792027B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07792027B2
公开(公告)日：2010-09-07
申请号：US11369125
申请日：2006-03-06
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

8. 发明授权

US07715419B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07715419B2
公开(公告)日：2010-05-11
申请号：US11368776
申请日：2006-03-06
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports of a network interface. A high priority buffer and a low priority buffer can be assigned to each port of the network interface. The network interface can perform packet prioritization through buffer selection based on priority. High priority packets will be transmitted to an ingress packet processor before low priority packets for a given port.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者接收来自网络的分组，并通过网络接口的一个或多个连接端口将分组发送到网络。可以将高优先级缓冲区和低优先级缓冲区分配给网络接口的每个端口。网络接口可以通过基于优先级的缓冲区选择来执行分组优先级。高优先级数据包将在给定端口的低优先级数据包之前传输到入口数据包处理器。

9. 发明申请

US20080117913A1 Pipelined Packet Switching and Queuing Architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US20080117913A1
公开(公告)日：2008-05-22
申请号：US11931527
申请日：2007-10-31
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

10. 发明授权

US08571024B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US08571024B2
公开(公告)日：2013-10-29
申请号：US12952601
申请日：2010-11-23
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/28 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

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