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1. 发明申请

US20080138075A1 System and method for providing an Ethernet interface 有权
标题翻译：提供以太网接口的系统和方法
公开(公告)号：US20080138075A1
公开(公告)日：2008-06-12
申请号：US12001551
申请日：2007-12-11
申请人： Mark A. Gustlin , Oded Trainin , Luca Della Chiesa
发明人： Mark A. Gustlin , Oded Trainin , Luca Della Chiesa
IPC分类号： H04B10/00
CPC分类号： H04L65/4069 , H04B10/516 , H04J14/02 , H04L47/10 , H04L47/13 , H04L47/39 , H04L49/352
摘要： An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes.In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.
摘要翻译：提供了一种包括n个通信信道，以及m个通信媒体接口和v个虚拟通道的装置。 V是m和n的最小公倍数的正整数倍。信息流被传送到在所有v虚拟通道之间划分的数据和对准块，该块从虚拟通道传送到通信信道上。这些块在通信信道上被接收。每个通信信道传输跨所有v虚拟通道条带化的块的不同部分。在更具体的实施例中，v> = n> = m。通信媒体接口可以是电气和光学的。每个通信信道可以包括每秒操作至少5千兆位的SerDes接口。此外，m个通信媒体接口中的每一个被配置为通过单个光纤发送不同的信息流。

2. 发明授权

US08949699B1 Circuit for forward error correction encoding of data blocks across multiple data lanes 有权
标题翻译：用于跨多个数据通道的数据块的前向纠错编码的电路
公开(公告)号：US08949699B1
公开(公告)日：2015-02-03
申请号：US13598548
申请日：2012-08-29
申请人： Mark A. Gustlin
发明人： Mark A. Gustlin
IPC分类号： H03M13/00
CPC分类号： H03M13/333 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2707
摘要： In one embodiment, a method for communicating a sequence of data bits is provided. FEC coding is performed on a received sequence of data bits to produce an FEC coded sequence formatted for a first set of N data lanes. The FEC coded sequence includes FEC data blocks, in which each FEC data block has a plurality of data symbols. Alignment markers are added to the FEC coded sequence and the FEC coded sequence is multiplexed to produce a multiplexed sequence formatted for a second set of M data lanes. The multiplexing is performed only at boundaries between the data symbols or the alignment markers. The multiplexed sequence is transmitted on M data lanes.
摘要翻译：在一个实施例中，提供了一种用于传送数据位序列的方法。对接收的数据比特序列执行FEC编码，以产生为第一组N个数据通道格式化的FEC编码序列。 FEC编码序列包括FEC数据块，其中每个FEC数据块具有多个数据符号。对准标记被添加到FEC编码序列，并且FEC编码序列被多路复用以产生为第二组M数据通道格式化的多路复用序列。仅在数据符号或对准标记之间的边界处执行复用。多路复用序列在M个数据通道上传输。

3. 发明授权

US07606158B2 Hierarchical flow control for router ATM interfaces 有权
标题翻译：路由器ATM接口的分层流控制
公开(公告)号：US07606158B2
公开(公告)日：2009-10-20
申请号：US10949916
申请日：2004-09-24
申请人： Guy C. Fedorkow , Kenneth H. Potter, Jr. , Mark A. Gustlin , Christopher J. Kappler , Robert T. Olsen
发明人： Guy C. Fedorkow , Kenneth H. Potter, Jr. , Mark A. Gustlin , Christopher J. Kappler , Robert T. Olsen
IPC分类号： H04J1/16
CPC分类号： H04L47/10 , H04L12/5601 , H04L47/266 , H04L2012/562 , H04L2012/5679 , H04L2012/5681
摘要： Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.
摘要翻译：现在公开的是一种用于在包含ATM接口的网络通信设备中将带宽分配和分组调度的控制返回到路由引擎的装置和方法。通过从每个虚拟路径（VP）添加第二流量控制反馈信号来增加虚拟电路（VC）流量控制。当流量累积在足够的VC上以保持VP忙时，VP流控制用于暂停给定VP上所有VC的调度。采用新的分组分段器来分段业务，同时保持接收到分组业务的先入先出（FIFO）顺序。可以使用两级（每VC和每VP）调度层次来实现本发明的实施例，或者可以使用多级调度层次可能需要的流控制反馈导出调度级别。

4. 发明授权

US09014563B2 System and method for providing an Ethernet interface 有权
标题翻译：提供以太网接口的系统和方法
公开(公告)号：US09014563B2
公开(公告)日：2015-04-21
申请号：US12001551
申请日：2007-12-11
申请人： Mark A. Gustlin , Oded Trainin , Luca Della Chiesa
发明人： Mark A. Gustlin , Oded Trainin , Luca Della Chiesa
IPC分类号： H04J14/08 , H04L12/801 , H04B10/00 , H04J14/02
CPC分类号： H04L65/4069 , H04B10/516 , H04J14/02 , H04L47/10 , H04L47/13 , H04L47/39 , H04L49/352
摘要： An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes.In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.
摘要翻译：提供了一种包括n个通信信道，以及m个通信媒体接口和v个虚拟通道的装置。 V是m和n的最小公倍数的正整数倍。信息流被传送到在所有v虚拟通道之间划分的数据和对准块，该块从虚拟通道传送到通信信道上。这些块在通信信道上被接收。每个通信信道传输跨所有v虚拟通道条带化的块的不同部分。在更具体的实施例中，v> = n> = m。通信媒体接口可以是电气和光学的。每个通信信道可以包括每秒操作至少5千兆位的SerDes接口。此外，m个通信媒体接口中的每一个被配置为通过单个光纤发送不同的信息流。

5. 发明授权

US08699523B2 Inducing protocol violations for identifying a stream of information 有权
标题翻译：诱导违反协议以识别信息流
公开(公告)号：US08699523B2
公开(公告)日：2014-04-15
申请号：US13195768
申请日：2011-08-01
申请人： Mark A. Gustlin
发明人： Mark A. Gustlin
IPC分类号： H04J3/24 , H04J3/04
CPC分类号： H04J3/0605 , H04L1/0082
摘要： In one embodiment, protocol violations of a particular protocol are induced at one or more predetermined intervals within a particular stream of information encoded according to the particular protocol in order to produce a marked particular stream of information for use in subsequent identification of the marked particular stream of information. The marked stream is multiplexed or otherwise communicated to a second device. The second device detects, and typically corrects, the induced protocol violations. And based on which stream of information included the induced protocol violations and the multiplexing/distribution pattern of the other streams of information, the second device can identify which stream is which and process or forward accordingly.
摘要翻译：在一个实施例中，在根据特定协议编码的特定信息流内以一个或多个预定间隔诱发特定协议的协议违反，以便产生标记的特定信息流，用于随后识别标记的特定流的信息。标记的流被复用或以其他方式传送到第二设备。第二个设备检测并通常纠正诱发的协议违规。并且基于哪个信息流包括感应协议违反和其他信息流的复用/分配模式，第二设备可以识别哪个流是相应地哪个和哪个和哪个进程或转发的。

6. 发明授权

US07433988B2 Port adapter for high-bandwidth bus 有权
标题翻译：用于高带宽总线的端口适配器
公开(公告)号：US07433988B2
公开(公告)日：2008-10-07
申请号：US11818006
申请日：2007-06-12
申请人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , Mohammed I. Tatar
发明人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , Mohammed I. Tatar
IPC分类号： G06F13/14 , H04B7/00 , H04L12/66
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.
摘要翻译：公开了一种用于将零个或多个网络接口连接到具有SPI-4总线的主机系统的端口适配器。端口适配器包括零个或多个网络接口; 耦合到主机系统的SPI-4总线以在主机和网络接口之间提供通信信道; 耦合到所述主机系统的用于控制和监视所述端口适配器的控制总线; 以及将SPI-4总线和控制总线连接到网络接口的接口逻辑。提供了用于选择和使用用于各种联网技术的小的多种不同分组格式之一的方法，使得端口适配器可以隐藏其从主机系统处理的技术的细节，并且用于操作主机系统的SPI-4总线基于端口适配器的带宽要求，以几种速度之一。

7. 发明申请

US20130034111A1 Inducing Protocol Violations For Identifying a Stream of Information 有权
标题翻译：引发协议违规用于识别信息流
公开(公告)号：US20130034111A1
公开(公告)日：2013-02-07
申请号：US13195768
申请日：2011-08-01
申请人： Mark A. GUSTLIN
发明人： Mark A. GUSTLIN
IPC分类号： H04J99/00
CPC分类号： H04J3/0605 , H04L1/0082
摘要： In one embodiment, protocol violations of a particular protocol are induced at one or more predetermined intervals within a particular stream of information encoded according to the particular protocol in order to produce a marked particular stream of information for use in subsequent identification of the marked particular stream of information. The marked stream is multiplexed or otherwise communicated to a second device. The second device detects, and typically corrects, the induced protocol violations. And based on which stream of information included the induced protocol violations and the multiplexing/distribution pattern of the other streams of information, the second device can identify which stream is which and process or forward accordingly.
摘要翻译：在一个实施例中，在根据特定协议编码的特定信息流内以一个或多个预定间隔诱发特定协议的协议违反，以便产生标记的特定信息流，用于随后识别标记的特定流的信息。标记的流被复用或以其他方式传送到第二设备。第二个设备检测并通常纠正诱发的协议违规。并且基于哪个信息流包括感应协议违反和其他信息流的复用/分配模式，第二设备可以识别哪个流是相应地哪个和哪个和哪个进程或转发的。

8. 发明授权

US07310695B2 Port adapter for high-bandwidth bus 有权
公开(公告)号：US07310695B2
公开(公告)日：2007-12-18
申请号：US11502965
申请日：2006-08-11
申请人： Garry P. Epps , Mark A. Gustlin , Mohammed I. Tatar
发明人： Garry P. Epps , Mark A. Gustlin , Mohammed I. Tatar
IPC分类号： G06F13/14 , H04B7/00 , H04L12/66
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

9. 发明授权

US07111102B2 Port adapter for high-bandwidth bus 有权
公开(公告)号：US07111102B2
公开(公告)日：2006-09-19
申请号：US10680842
申请日：2003-10-06
申请人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
发明人： David Doak , Garry P. Epps , Guy Fedorkow , Mark A. Gustlin , Steven P. Holmes , Randall A. Johnson , Promode Nedungadi , John P. Prokopik , Mohammed I. Tatar , Michael J. Taylor
IPC分类号： G06F13/14 , H04L9/00
CPC分类号： H04L12/5692 , G06F13/387 , H04J3/1617 , Y10S370/912
摘要： A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

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