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1. 发明授权

US06971039B2 DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second memory modules 失效
标题翻译： DDR到SDR转换，其解码读取和写入访问，并将延迟的命令转发到第一和第二存储器模块
公开(公告)号：US06971039B2
公开(公告)日：2005-11-29
申请号：US10075539
申请日：2002-02-14
申请人： Gunnar Krause , Sebastian Kuhne , Bernd Klehn
发明人： Gunnar Krause , Sebastian Kuhne , Bernd Klehn
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4093 , G06F5/00
CPC分类号： G11C7/1084 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C11/4093
摘要： A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.
摘要翻译：描述了一种存储器模块，其在外部具有DDR SDRAM的功能并且包含两组常规SDRAM。转换装置提供时钟信号，命令和数据的转换。转换装置包含用于地址和命令的转换开关，延迟锁定环路和缓冲存储器，并且还包括以适当方式由延迟锁定环路驱动的数据。

2. 发明授权

US06865707B2 Test data generator 失效
标题翻译：测试数据生成器
公开(公告)号：US06865707B2
公开(公告)日：2005-03-08
申请号：US10109657
申请日：2002-04-01
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Luepke , Jochen Mueller , Peter Poechmueller , Michael Schittenhelm
IPC分类号： G01R31/3183 , G11C29/14 , G11C29/36 , G01R31/28 , G06F11/00
CPC分类号： G11C29/14 , G01R31/3183 , G11C29/36
摘要： Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.
摘要翻译：用于产生用于测试具有倍频电路的电路的测试数据模式的测试数据发生器，其增加由测试单元以特定时钟倍频因子接收的输入时钟信号的低时钟频率。还提供了多个数据寄存器，用于存储从数据寄存器读取的测试数据字，以及多路复用器，以一种方式将通过从输出时钟信号的高时钟频率从数据寄存器读取的测试数据字切换到数据总线取决于多位置寄存器选择控制数据向量的寄存器选择控制基准。

3. 发明授权

US06779124B2 Selectively deactivating a first control loop in a dual control loop circuit during data transmission 有权
标题翻译：在数据传输期间选择性地禁用双控制回路中的第一控制回路
公开(公告)号：US06779124B2
公开(公告)日：2004-08-17
申请号：US09811881
申请日：2001-03-19
申请人： Rainer Höhler , Gunnar Krause
发明人： Rainer Höhler , Gunnar Krause
IPC分类号： G06F104
CPC分类号： G11C7/1072 , G06F13/4243 , G11C7/22
摘要： The circuit has a clock input for supplying a first clock signal and a clock generator for generating a second clock signal, said clock generator being phase-locked with respect to the first clock signal. The clock output of the clock generator is connected to a control input of a data transmission unit used for outputting data from the circuit and/or for reading into the circuit essentially in synchronism with the first clock signal. The clock generator has at least two control loops connected in succession which are used for controlling the phase angle of the second clock signal, the first control loop being used to generate from the first clock signal at least two intermediate clock signals, each of which has a particular phase angle with respect to the first clock signal, and the second control loop being used to generate the second clock signal from the intermediate clock signals. The first control loop is deactivated during the transmission of data by the data transmission unit, so that the control of the phase angle of the intermediate clock signals is interrupted.
摘要翻译：电路具有用于提供第一时钟信号的时钟输入和用于产生第二时钟信号的时钟发生器，所述时钟发生器相对于第一时钟信号被锁相。时钟发生器的时钟输出连接到用于从电路输出数据和/或用于与第一时钟信号同步地读入电路的数据传输单元的控制输入。时钟发生器具有连续连接的至少两个控制回路，用于控制第二时钟信号的相位角，第一控制回路用于从第一时钟信号产生至少两个中间时钟信号，每个中间时钟信号具有相对于第一时钟信号的特定相位角，并且第二控制环用于从中间时钟信号产生第二时钟信号。在由数据传输单元发送数据期间，第一控制环路被去激活，使得中间时钟信号的相位角的控制被中断。

4. 发明授权

US06556492B2 System for testing fast synchronous semiconductor circuits 失效
公开(公告)号：US06556492B2
公开(公告)日：2003-04-29
申请号：US09907695
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C700
CPC分类号： G11C29/56
摘要： The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

5. 发明授权

US06459649B2 Address generator for generating addresses for an on-chip trim circuit 失效
标题翻译：用于产生片上微调电路地址的地址发生器
公开(公告)号：US06459649B2
公开(公告)日：2002-10-01
申请号：US09854258
申请日：2001-05-10
申请人： Gunnar Krause , Wolfgang Spirkl
发明人： Gunnar Krause , Wolfgang Spirkl
IPC分类号： G11C800
CPC分类号： G11C29/02 , G11C5/147 , G11C8/04 , G11C29/021 , G11C29/028
摘要： An address generator for generating addresses for an on-chip trim circuit for tuning a reference voltage produced on a semiconductor chip. The address generator contains a particular number of stages, each made up of a memory latch, which, upon a control signal supplied to a control input of the address generator, and upon a clock signal applied to a clock input of the address generator, can optionally be operated as a synchronous counter or as a shift register. The number M being greater than or equal to 1.
摘要翻译：一种用于产生用于调整在半导体芯片上产生的参考电压的片上微调电路的地址的地址发生器。地址生成器包含特定数量的级，每个级由存储器锁存器构成，当存储器锁存器被提供给地址发生器的控制输入端的控制信号时，以及施加到地址发生器的时钟输入端的时钟信号，可选地作为同步计数器或移位寄存器来操作。数字M大于或等于1。

6. 发明授权

US06728147B2 Method for on-chip testing of memory cells of an integrated memory circuit 有权
标题翻译：用于片上测试集成存储器电路的存储单元的方法
公开(公告)号：US06728147B2
公开(公告)日：2004-04-27
申请号：US10202690
申请日：2002-07-24
申请人： Peter Beer , Jochen Kallscheuer , Gunnar Krause
发明人： Peter Beer , Jochen Kallscheuer , Gunnar Krause
IPC分类号： G11C700
CPC分类号： G11C29/12 , G11C29/10
摘要： A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.
摘要翻译：用于片上测试集成存储器电路的单元阵列的存储单元的方法包括将不同的数据模式写入存储器单元并从存储器单元读取不同的数据模式以便测试存储器单元。基本数据模式存储在数据字寄存器中，并通过应用由控制器提供的数据控制信号读出。除了基本数据模式之外，通过使用数据控制信号，以目标方式访问与基本数据模式不同并存储在数据字寄存器部分中的至少一个另外的数据模式。因此，测试迅速进行，并产生广泛的测试信息。

7. 发明授权

US06721904B2 System for testing fast integrated digital circuits, in particular semiconductor memory modules 失效
标题翻译：用于测试快速集成数字电路的系统，特别是半导体存储器模块
公开(公告)号：US06721904B2
公开(公告)日：2004-04-13
申请号：US09907693
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： H02H305
CPC分类号： G11C29/12015 , G11C29/48 , G11C29/56012
摘要： The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.
摘要翻译：本发明涉及一种用于测试快速集成数字电路，特别是半导体模块（例如SDRAM）的系统。为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度，同时大规模生产所需的测试系统的高度并行性，将额外的半导体电路模块（BOST模块）插入到信号中标准测试设备和要测试的SDRAM之间的路径。该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率，并且根据测试信号来确定用于测试SDRAM模块的控制信号，地址和数据背景的信号序列设备以及在测试前编程的寄存器内容，在BOST模块中。

8. 发明授权

US06612738B2 Method for determining the temperature of a semiconductor chip and semiconductor chip with temperature measuring configuration 有权
标题翻译：用于通过温度测量配置确定半导体芯片和半导体芯片的温度的方法
公开(公告)号：US06612738B2
公开(公告)日：2003-09-02
申请号：US09801963
申请日：2001-03-08
申请人： Peter Beer , Manfred Dobler , Gunnar Krause
发明人： Peter Beer , Manfred Dobler , Gunnar Krause
IPC分类号： G01K701
CPC分类号： G01K7/01 , G01R31/30
摘要： In order to be able to determine precisely a temperature of a semiconductor chip, in particular a semiconductor memory, during active operation, a temperature-dependent diode structure of the chip is connected to four chip terminals using four-conductor connection technology. In this manner, an inexpensive and accurate measuring mechanism is provided for measuring the temperature.
摘要翻译：为了能够精确地确定半导体芯片，特别是半导体存储器的温度，在有源操作期间，使用四导体连接技术将芯片的温度依赖二极管结构连接到四个芯片端子。以这种方式，提供了用于测量温度的便宜且精确的测量机构。

9. 发明授权

US06274410B1 Method of programming a semiconductor memory 有权
公开(公告)号：US06274410B1
公开(公告)日：2001-08-14
申请号：US09729068
申请日：2000-12-04
申请人： Holger Göbel , Gunnar Krause
发明人： Holger Göbel , Gunnar Krause
IPC分类号： H01L2182
摘要： A method of programming a semiconductor memory includes forming a multiplicity of fuse links in at least two mutually parallel planes in a semiconductor body, and separating the fuse links from one another with an electrical insulator. It also includes irradiating a selected fuse link with at least two laser beams and melting the selected fuse link by crossing the laser beams at the selected fuse link.

10. 发明授权

US6157589A Dynamic semiconductor memory device and method for initializing a dynamic semiconductor memory device 有权
标题翻译：用于初始化动态半导体存储器件的动态半导体存储器件和方法
公开(公告)号：US6157589A
公开(公告)日：2000-12-05
申请号：US343431
申请日：1999-06-30
申请人： Gunnar Krause
发明人： Gunnar Krause
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A dynamic semiconductor memory device of a random access type has an initialization circuit that controls the switching-on operation of the semiconductor memory device and of its circuit components. The initialization circuit supplies a supply voltage stable signal once the supply voltage has been stabilized after the switching-on of the semiconductor memory device. The initialization circuit has an enable circuit that receives the supply voltage stable signal and further command signals externally applied to the semiconductor memory device. The enable circuit supplies an enable signal after a predetermined proper initialization sequence of the command signals applied to the semiconductor memory device is identified. The enable signal effects the unlatching of a control circuit provided for the proper operation of the semiconductor memory device.
摘要翻译：随机存取型的动态半导体存储器件具有控制半导体存储器件及其电路元件的接通操作的初始化电路。一旦电源电压在半导体存储器件接通之后稳定，初始化电路就提供电源电压稳定信号。该初始化电路具有一个使能电路，其接收电源电压稳定信号以及从外部施加到半导体存储器件的另外的指令信号。在识别出施加到半导体存储器件的命令信号的预定正确初始化序列之后，使能电路提供使能信号。使能信号影响为半导体存储器件的正常工作提供的控制电路的解锁。

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