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1. 发明授权

US07372749B2 Methods for repairing and for operating a memory component 失效
标题翻译：修复和操作存储器组件的方法
公开(公告)号：US07372749B2
公开(公告)日：2008-05-13
申请号：US11274059
申请日：2005-11-14
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C11/401 , G11C29/816
摘要： In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner that a write or read access to the weak regular memory cell is simultaneously also effected for a redundant memory cell in order to jointly read from, or write to, the weak regular memory cell and the redundant memory cell.
摘要翻译：在修复存储器组件的方法中，确定常规存储单元的数据保留时间。确定具有比预定极限值短的数据保留时间的弱常规存储单元。设备被编程为使得对于冗余存储器单元同时也对弱规则存储单元进行写入或读取访问，以便联合从弱常规存储器单元和冗余存储器单元读取或向其写入。

2. 发明授权

US07248067B2 Semiconductor device with test circuit disconnected from power supply connection 有权
标题翻译：带有测试电路的半导体器件与电源连接断开
公开(公告)号：US07248067B2
公开(公告)日：2007-07-24
申请号：US10946024
申请日：2004-09-21
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G01R31/26
CPC分类号： G01R31/3012 , G01R31/3187
摘要： A semiconductor device with a test circuit disconnected from a power supply connection to reduce leakage current, and a method of manufacture thereof. The test circuit may be used to test functional circuits on the semiconductor device, and after the tests are completed, the test circuit is disconnected from the power supply connection. The test circuit is powered by contacting a test pad with a probe that supplies power to the test circuit, in one embodiment. In another embodiment, the test circuit is disconnected from the power supply using a laser to blow a fuse in the path of the power supply connection for the test circuit. Optional features include a bleeder device coupled to the power supply input of the test circuit, and logic circuitry for setting the outputs of the test circuit to a predetermined state coupled to the outputs of the test circuit.
摘要翻译：具有与电源连接断开的测试电路以减少漏电流的半导体器件及其制造方法。测试电路可用于测试半导体器件上的功能电路，测试完成后，测试电路与电源连接断开。在一个实施例中，测试电路通过使测试焊盘与向测试电路供电的探针接触来供电。在另一个实施例中，使用激光将测试电路与电源断开，以便在用于测试电路的电源连接的路径中熔断熔断器。可选特征包括耦合到测试电路的电源输入端的泄放装置和用于将测试电路的输出设置为耦合到测试电路的输出的预定状态的逻辑电路。

3. 发明申请

US20070090500A1 Housed DRAM chip for high-speed applications 审中-公开
标题翻译：用于高速应用的嵌入式DRAM芯片
公开(公告)号：US20070090500A1
公开(公告)日：2007-04-26
申请号：US11581068
申请日：2006-10-16
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： H01L23/495
CPC分类号： H01L23/66 , G11C5/025 , G11C5/06 , H01L23/13 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/05599 , H01L2224/48227 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/10161 , H01L2924/15311 , H01L2224/45099 , H01L2924/00
摘要： A housed DRAM chip includes a DRAM chip and a housing substrate. The DRAM chip is arranged on the housing substrate such that shorter conductive connections between the chip pads of the DRAM chip and external housing connections can be achieved for high data transmission speeds.
摘要翻译：封装的DRAM芯片包括DRAM芯片和外壳基板。 DRAM芯片布置在壳体基板上，使得可以实现DRAM芯片的芯片焊盘和外部壳体连接之间的更短的导电连接，用于高数据传输速度。

4. 发明申请

US20060133159A1 Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose 有权
标题翻译：用于在线对上发送和接收数据信号的方法，以及用于此目的的发送和接收电路
公开(公告)号：US20060133159A1
公开(公告)日：2006-06-22
申请号：US11284139
申请日：2005-11-21
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： H04L25/49
摘要： Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of first and second signal levels is applied to the first transmission line, and a reference signal which changes between a first and a second reference level only when a level change between the first and the second signal level is suppressed between two successive signal levels of the data signal on the first transmission line is applied to the second transmission line.
摘要翻译：提供了用于在具有第一传输线和第二传输线的线对上发送和接收数据信号的装置和方法。在一个实施例中，表示要通过第一和第二信号电平序列发射的数据的数据信号被施加到第一传输线，以及参考信号，其仅在第一和第二参考电平在第一传输线上的数据信号的两个连续信号电平被施加到第二传输线之间，抑制了第一和第二信号电平之间的电平变化。

5. 发明申请

US20060049515A1 Memory module having memory chips protected from excessive heat 有权
标题翻译：具有防止过热的存储器芯片的存储器模块
公开(公告)号：US20060049515A1
公开(公告)日：2006-03-09
申请号：US11211893
申请日：2005-08-25
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： H01L23/34 , H01L23/02
CPC分类号： G11C5/04 , G11C5/143 , H05K1/0201 , H05K1/181 , H05K2201/062 , H05K2201/066 , H05K2201/09063 , H05K2201/09972
摘要： The invention relates to a memory module having a printed circuit board; having one or more memory chips which are arranged in a first region of the printed circuit board and are contact-connected by the printed circuit board; having a buffer chip for driving the memory chips and for communicating with a system that is external to the memory module, the buffer chip being arranged in a second region of the printed circuit board and being contact-connected by the printed circuit board; wherein the first and second regions of the printed circuit board are essentially thermally decoupled from one another.
摘要翻译：本发明涉及一种具有印刷电路板的存储模块; 具有布置在印刷电路板的第一区域中并通过印刷电路板接触连接的一个或多个存储器芯片; 具有用于驱动存储芯片并用于与存储器模块外部的系统进行通信的缓冲芯片，缓冲芯片布置在印刷电路板的第二区域中并通过印刷电路板接触连接; 其中印刷电路板的第一和第二区域基本上彼此热分离。

6. 发明申请

US20050281076A1 Memory circuit comprising redundant memory areas 失效
标题翻译：存储电路包括冗余存储区
公开(公告)号：US20050281076A1
公开(公告)日：2005-12-22
申请号：US11145256
申请日：2005-06-03
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C11/00
CPC分类号： G11C29/787 , G11C2229/743 , G11C2229/746 , G11C2229/763 , G11C2229/766
摘要： The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a first setting state, to address the assigned redundant memory area in the event of addressing of the regular memory area with a memory address determined by the first setting state, each redundancy circuit, in a second setting state, addressing the assigned redundant memory area in a manner dependent on an activation signal.
摘要翻译：本发明涉及包括常规存储区域和冗余存储器区域的存储器电路，每种情况下都将冗余电路分配给冗余存储区域，每个冗余电路在第一设置状态下依次具有永久可设置的存储元件，以寻址所分配的在通过第一设置状态确定的存储器地址寻址常规存储器区域的情况下，在第二设置状态下，每个冗余电路以取决于激活信号的方式寻址所分配的冗余存储器区域。

7. 发明申请

US20050216808A1 Method and circuit arrangement for testing electrical modules 有权
标题翻译：用于测试电气模块的方法和电路布置
公开(公告)号：US20050216808A1
公开(公告)日：2005-09-29
申请号：US11073814
申请日：2005-03-07
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G01R31/3193 , G06F11/00 , G11C29/00 , G11C29/38
CPC分类号： G11C29/38 , G01R31/318505 , G01R31/31917 , G01R31/3193 , G11C2029/0401
摘要： The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated for the purpose of displaying test assessments. According to one embodiment of the invention, to supply the desired responses, a reference module produced with the same design and technology as the test specimen and tested as entirely satisfactory is utilized. The same test pattern as for the test specimen is applied to the reference module. The invention furthermore relates to circuit arrangements for carrying out this method, in particular for testing data memories.
摘要翻译：本发明涉及一种用于测试电气模块的方法。将输入信号的测试图案应用于要作为测试样本测试的每个模块，并将测试样本对测试图案的实际响应与期望的响应进行比较。对比较结果进行评估，以显示测试评估。根据本发明的一个实施例，为了提供所需的响应，利用与测试样本相同的设计和技术生产并且完全令人满意的测试的参考模块。将与试样相同的测试图案应用于参考模块。本发明还涉及用于执行该方法的电路装置，特别是用于测试数据存储器。

8. 发明授权

US06522578B2 Method for preventing electromigration in an MRAM 有权
标题翻译：防止MRAM中电迁移的方法
公开(公告)号：US06522578B2
公开(公告)日：2003-02-18
申请号：US09898791
申请日：2001-07-03
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C1114
CPC分类号： G11C11/16 , G11C11/15
摘要： A method for preventing electromigration in a magnetic random access memory (MRAM) is described. In the method, after a programming step, a signal which compensates for the electromigration and has opposite polarity is fed to the wordline and bitline in such a way that programming does not occur in the memory cells.
摘要翻译：描述了一种用于防止磁随机存取存储器（MRAM）中的电迁移的方法。在该方法中，在编程步骤之后，补偿电迁移并且具有相反极性的信号被馈送到字线和位线，使得在存储器单元中不发生编程。

9. 发明授权

US06504751B2 Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory 有权
公开(公告)号：US06504751B2
公开(公告)日：2003-01-07
申请号：US09898224
申请日：2001-07-03
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： An integrated memory has memory cells with a magnetoresistive storage property. The memory cells are connected in each case between column lines and row lines. For reading a data signal of a memory cell connected to a row line, one of the row lines is connected in a selection circuit to a terminal for a selection signal. The other row lines are driven in such a way that they are electrically isolated in the selection circuit for the reading of the data signal. As a result, a comparatively reliable reading operation is possible.

10. 发明授权

US5859801A Flexible fuse placement in redundant semiconductor memory 失效
标题翻译：冗余半导体存储器中的灵活熔丝放置
公开(公告)号：US5859801A
公开(公告)日：1999-01-12
申请号：US825312
申请日：1997-03-28
申请人： Peter Poechmueller
发明人： Peter Poechmueller
IPC分类号： G11C29/04 , G11C19/00 , G11C29/00 , G11C7/00 , G11C8/00
CPC分类号： G11C29/789 , G11C19/00 , G11C29/80 , G11C29/802 , G11C29/808
摘要： Disclosed is a semiconductor memory having a main memory cell array and redundant memory cells, with a plurality of fuses that can be physically separated from their associated fuse latches. Physical separation is possible by incorporating serial transfer circuitry to serially transfer fuse data from the fuses towards the latches. As a result, only a small number of wires are needed to connect the fuses to the fuse latches, allowing for flexible fuse placement within the memory.
摘要翻译：公开了一种具有主存储单元阵列和冗余存储单元的半导体存储器，其具有可与其相关联的熔丝锁存器物理分离的多个保险丝。通过并入串行传输电路将保险丝数据从保险丝串联传输到锁存器，实现物理分离。因此，只需要少量电线将保险丝连接到保险丝锁存器，从而允许将灵活的保险丝放置在存储器内。

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