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1. 发明授权

US06728147B2 Method for on-chip testing of memory cells of an integrated memory circuit 有权
标题翻译：用于片上测试集成存储器电路的存储单元的方法
公开(公告)号：US06728147B2
公开(公告)日：2004-04-27
申请号：US10202690
申请日：2002-07-24
申请人： Peter Beer , Jochen Kallscheuer , Gunnar Krause
发明人： Peter Beer , Jochen Kallscheuer , Gunnar Krause
IPC分类号： G11C700
CPC分类号： G11C29/12 , G11C29/10
摘要： A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.
摘要翻译：用于片上测试集成存储器电路的单元阵列的存储单元的方法包括将不同的数据模式写入存储器单元并从存储器单元读取不同的数据模式以便测试存储器单元。基本数据模式存储在数据字寄存器中，并通过应用由控制器提供的数据控制信号读出。除了基本数据模式之外，通过使用数据控制信号，以目标方式访问与基本数据模式不同并存储在数据字寄存器部分中的至少一个另外的数据模式。因此，测试迅速进行，并产生广泛的测试信息。

2. 发明授权

US06858447B2 Method for testing semiconductor chips 有权
标题翻译：半导体芯片测试方法
公开(公告)号：US06858447B2
公开(公告)日：2005-02-22
申请号：US10151990
申请日：2002-05-21
申请人： Udo Hartmann , Jochen Kallscheuer , Peter Beer
发明人： Udo Hartmann , Jochen Kallscheuer , Peter Beer
IPC分类号： G01R31/28 , G01R31/26 , G01R31/30 , G06F11/26 , G11C29/12 , G11C29/14 , G11C29/46 , H01L21/822 , H01L27/04 , H01L21/66 , G06F17/50
CPC分类号： G11C29/14 , G01R31/30 , G06F11/26 , G06F2201/83 , G11C29/46
摘要： A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.
摘要翻译：描述了用于测试半导体芯片，特别是半导体存储器芯片的方法。其中，在要测试的芯片中，至少设置一个测试模式，芯片中执行测试模式，芯片输出测试结果。条件是，在设置之后和执行测试模式之前，执行检查模式，其中以定义的格式读出设置在芯片中的测试模式的状态。

3. 发明授权

US06612738B2 Method for determining the temperature of a semiconductor chip and semiconductor chip with temperature measuring configuration 有权
标题翻译：用于通过温度测量配置确定半导体芯片和半导体芯片的温度的方法
公开(公告)号：US06612738B2
公开(公告)日：2003-09-02
申请号：US09801963
申请日：2001-03-08
申请人： Peter Beer , Manfred Dobler , Gunnar Krause
发明人： Peter Beer , Manfred Dobler , Gunnar Krause
IPC分类号： G01K701
CPC分类号： G01K7/01 , G01R31/30
摘要： In order to be able to determine precisely a temperature of a semiconductor chip, in particular a semiconductor memory, during active operation, a temperature-dependent diode structure of the chip is connected to four chip terminals using four-conductor connection technology. In this manner, an inexpensive and accurate measuring mechanism is provided for measuring the temperature.
摘要翻译：为了能够精确地确定半导体芯片，特别是半导体存储器的温度，在有源操作期间，使用四导体连接技术将芯片的温度依赖二极管结构连接到四个芯片端子。以这种方式，提供了用于测量温度的便宜且精确的测量机构。

4. 发明授权

US08051048B2 System and method for automated transfer and evaluation of the quality of mass data of a technical process or a technical project 有权
标题翻译：用于自动传输和评估技术过程或技术项目质量数据质量的系统和方法
公开(公告)号：US08051048B2
公开(公告)日：2011-11-01
申请号：US11785859
申请日：2007-04-20
申请人： Peter Beer , Andreas Liefeldt
发明人： Peter Beer , Andreas Liefeldt
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06Q10/06
摘要： The invention relates to a system and a method for automated transfer and subsequent evaluation of the quality of mass data of a technical process or a technical project in a standardized environment (70) of one or more data processing devices with an assignment module (20) for allocating the mass data from one or more data sources (10) to structure elements in the standardized environment of the data processing device (70) and for generating a defined mapping of the mass data to be read in. The assignment module (20) interacts with a read-in module (30), into which the mass data can be read in an automated operation according to the selected assignment. The data read in can be fed to a checking module (40) for automated checking and/or for generation of a report for evaluation of the quality of the measured data read in. The check results generated by the checking module (40) can be fed to a processing module (60) for automated logging in predefined structures, and the results of the check can be transferred into the standardized environment (70) of the data processing device.
摘要翻译：本发明涉及一种用于在具有分配模块（20）的一个或多个数据处理设备的标准化环境（70）中自动传送和随后评估技术过程或技术项目的质量数据质量的系统和方法，用于将来自一个或多个数据源（10）的质量数据分配给数据处理设备（70）的标准化环境中的结构元素，并用于生成要读入的质量数据的定义映射。分配模块（20）与读入模块（30）进行交互，根据所选择的分配，可以在自动操作中读取质量数据。读取的数据可以被馈送到检查模块（40），用于自动检查和/或生成用于评估读入的测量数据的质量的报告。由检查模块（40）生成的检查结果可以是馈送到处理模块（60），用于以预定结构进行自动日志记录，并且检查结果可以被传送到数据处理设备的标准化环境（70）。

5. 发明申请

US20090268505A1 Method of Operating an Integrated Circuit, and Integrated Circuit 审中-公开
标题翻译：操作集成电路和集成电路的方法
公开(公告)号：US20090268505A1
公开(公告)日：2009-10-29
申请号：US12108377
申请日：2008-04-23
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/1673 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2013/0078 , G11C2213/35 , G11C2213/71 , G11C2213/78 , G11C2213/79
摘要： According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistivity changing memory cells connected in parallel is provided. The method includes: choosing a resistivity changing memory cell having a first memory state out of the plurality of resistivity changing memory cells; measuring a first total resistance of the plurality of resistivity changing memory cells; setting the chosen resistivity changing memory cell to a second memory state, measuring a second total resistance of the plurality of resistivity changing memory cells; and determining the first memory state of the chosen resistivity changing memory cell in dependence on the first total resistance and the second total resistance.
摘要翻译：根据本发明的一个实施例，提供一种操作包括并联连接的多个电阻率变化存储单元的集成电路的方法。该方法包括：从多个电阻率变化存储单元中选择具有第一存储状态的电阻率变化存储单元; 测量所述多个电阻率变化存储单元的第一总电阻; 将所选择的电阻率变化存储单元设置为第二存储器状态，测量所述多个电阻率变化存储单元的第二总电阻; 以及根据第一总电阻和第二总电阻确定所选电阻率变化存储单元的第一存储状态。

6. 发明申请

US20080049525A1 Integrated Semiconductor Memory and Method for Operating an Integrated Semiconductor Memory 有权
标题翻译：用于操作集成半导体存储器的集成半导体存储器和方法
公开(公告)号：US20080049525A1
公开(公告)日：2008-02-28
申请号：US11828289
申请日：2007-07-25
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C29/24
CPC分类号： G11C29/846 , G11C29/808
摘要： In an embodiment, an integrated semiconductor memory includes a plurality of data lines via which data read out or to be read out from memory cells can be communicated, wherein the data lines comprise redundant data lines and non-redundant data lines, wherein the semiconductor memory has at least one data distributor line, and wherein a plurality of redundant data lines are connected up to the at least one data distributor line in such a way that in each case a redundant data line or a group of redundant data lines from the plurality of redundant data lines can be selected and can be connected to the at least one data distributor line.
摘要翻译：在一个实施例中，集成半导体存储器包括多个数据线，通过该数据线可以传送从存储器单元读出或要被读出的数据，其中数据线包括冗余数据线和非冗余数据线，其中半导体存储器具有至少一个数据分配器线，并且其中多个冗余数据线连接到所述至少一个数据分配器线，使得在每种情况下，来自所述多个数据分配器线的冗余数据线或一组冗余数据线可以选择冗余数据线并且可以连接到至少一个数据分配器线。

7. 发明申请

US20070276872A1 System and method for automated and structured transfer of technical documents and the management of the transferred documents in a database 审中-公开
标题翻译：技术文件的自动化和结构化转移和数据库中转移的文件的管理的系统和方法
公开(公告)号：US20070276872A1
公开(公告)日：2007-11-29
申请号：US11797879
申请日：2007-05-08
申请人： Peter Beer , Christian Kohlmeyer
发明人： Peter Beer , Christian Kohlmeyer
IPC分类号： G06F17/00 , G06F17/30 , G06F7/00
CPC分类号： G06F16/93
摘要： A system and a method are disclosed for the automated and structured transfer of technical documents and the management of the transferred documents in a database of an engineering process or an engineering project with at least one data source, in which the documents are stored in electronic form. One or more structures for storing the documents are implemented in the database. The structures are identifiable by means of an assigned identification feature. The data source interacts with an assignment module, which allocates each document a document identification number for unique assignment into one of the structures of the database. The data source further interacts with a sort module, which files the documents dependent on their document identification number in the structure identifiable by the identification feature in the database, and makes the documents available for further processing.
摘要翻译：公开了一种系统和方法，用于自动化和结构化地转移技术文件，以及在具有至少一个数据源的工程过程或工程项目的数据库中管理转移的文档，其中文档以电子形式存储。在数据库中实现用于存储文档的一个或多个结构。结构可以通过分配的识别特征来识别。数据源与分配模块进行交互，分配模块为每个文档分配用于唯一分配的文档标识号到数据库的一个结构中。数据源还与排序模块进行交互，分类模块根据数据库中的识别特征可识别的结构中的文档标识号来记录文档，并使文档可用于进一步处理。

8. 发明授权

US07302622B2 Integrated memory having a test circuit for functional testing of the memory 有权
标题翻译：具有用于对存储器进行功能测试的测试电路的集成存储器
公开(公告)号：US07302622B2
公开(公告)日：2007-11-27
申请号：US10920210
申请日：2004-08-18
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C29/26 , G11C29/40
CPC分类号： G11C29/38 , G11C29/26
摘要： An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.
摘要翻译：具有多个存储体的集成存储器包括用于对存储器进行功能测试的测试电路。多个次级读出放大器被分配给不同的存储体。测试电路包括用于产生读取比较数据的数据发生器。将多个比较电路分配给不同的存储体，以将从分配的存储体读出的测试数据与读取的比较数据进行比较。各个比较电路的第一输入可以连接到次级读出放大器而不插入读/写数据线。第二输入可以连接到读/写数据线以接收由数据发生器提供的读取比较数据。各个比较电路的输出信号取决于第一和第二输入的数据比较的比较结果。

9. 发明授权

US07162663B2 Test system and method for testing memory circuits 有权
标题翻译：用于测试存储器电路的测试系统和方法
公开(公告)号：US07162663B2
公开(公告)日：2007-01-09
申请号：US10676588
申请日：2003-10-01
申请人： Peter Beer , Alan Morgan
发明人： Peter Beer , Alan Morgan
IPC分类号： G06F11/00
CPC分类号： G11C29/26 , G11C2029/2602 , G11C2029/3602
摘要： A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.
摘要翻译：并行测试第一和第二存储器电路。可以根据电路选择信号来激活存储器电路，并且可以向第一和第二存储器电路施加控制信号。控制信号根据第一或第二存储器电路的激活而启动相应的存储器电路中的功能。在测试存储器电路时，将电路选择信号施加到第一存储器电路，并将反相电路选择信号施加到第二存储器电路，使得该功能根据电路在第一或第二存储器电路中启动选择信号。

10. 发明授权

US06737695B2 Memory module having a memory cell and method for fabricating the memory module 失效
标题翻译：具有存储单元的存储器模块和用于制造存储器模块的方法
公开(公告)号：US06737695B2
公开(公告)日：2004-05-18
申请号：US10156536
申请日：2002-05-28
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： H01L27108
CPC分类号： G11C11/405 , H01L27/108 , H01L27/10841 , H01L27/10864 , H01L29/945
摘要： A memory module and a method for fabricating the memory module are described. The memory module has a memory cell that is disposed in a vertical trench. The memory cell has a first and a second transistor connected in series and the first transistor is able to be turned on via a first word line and the second transistor is able to be turned on via a charge of a capacitor. The two transistors are connected between a voltage source and a bit line. In this way, the charge state of the capacitor is evaluated by the second transistor. If the capacitor has a positive charge, then the second transistor is turned on. If, moreover, the first word line is driven, then the first transistor is also turned on. As a consequence, the bit line is connected to the voltage source and supplied with a sufficiently strong signal for evaluation.
摘要翻译：描述存储器模块和用于制造存储器模块的方法。存储器模块具有设置在垂直沟槽中的存储单元。存储单元具有串联连接的第一和第二晶体管，并且第一晶体管能够经由第一字线导通，并且第二晶体管能够经由电容器的电荷导通。两个晶体管连接在电压源和位线之间。以这种方式，电容器的充电状态由第二晶体管评估。如果电容器具有正电荷，则第二晶体管导通。此外，如果第一字线被驱动，则第一晶体管也被接通。因此，位线连接到电压源并提供足够强的信号用于评估。

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