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1. 发明授权

US06556492B2 System for testing fast synchronous semiconductor circuits 失效
公开(公告)号：US06556492B2
公开(公告)日：2003-04-29
申请号：US09907695
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C700
CPC分类号： G11C29/56
摘要： The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

2. 发明授权

US07062690B2 System for testing fast synchronous digital circuits, particularly semiconductor memory chips 失效
公开(公告)号：US07062690B2
公开(公告)日：2006-06-13
申请号：US09907786
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/31905 , G11C29/56
摘要： A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

3. 发明授权

US06862702B2 Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices 失效
标题翻译：地址计数器用于寻址同步高频数字电路，特别是存储器件
公开(公告)号：US06862702B2
公开(公告)日：2005-03-01
申请号：US09907776
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/56 , G11C29/00
CPC分类号： G11C29/56
摘要： The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.
摘要翻译：新颖的地址计数器可以与用于测试数字电路的现有测试单元结合使用 - 用于寻址同步高频数字电路，特别是快速存储器件。在可编程偏移寄存器中提供地址偏移值，其中多路复用器电路和选择和组合电路基于由测试单元以低频和并联馈送的输入信号。可以以非常灵活的方式在高时钟频率下实现简单的地址改变和地址跳转。

4. 发明授权

US06871306B2 Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested 有权
标题翻译：用于读取和检查从要测试的存储器模块读出的数据响应信号的时间位置的方法和装置
公开(公告)号：US06871306B2
公开(公告)日：2005-03-22
申请号：US09907692
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/50 , G11C29/56 , G11C29/00
CPC分类号： G11C29/50 , G11C29/56
摘要： A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.
摘要翻译：一种用于读取和检查从要测试的存储器模块读出的数据响应的时间位置的方法和装置，特别是在DDR操作中操作的DRAM存储器。在测试接收机中，要测试的存储器模块的数据响应被锁存到具有被延迟的数据选通响应信号的数据锁存器中。产生对称时钟信号作为校准信号。校准信号用于校准相对于数据响应的延迟数据选通响应信号的时间位置。延迟的数据选通响应信号用于锁存数据响应。延迟时间在校准操作期间被编程到延迟器件中，并且还提供测量数据选通响应信号（DQS）和数据响应之间的精确时间关系。

5. 发明授权

US06721904B2 System for testing fast integrated digital circuits, in particular semiconductor memory modules 失效
标题翻译：用于测试快速集成数字电路的系统，特别是半导体存储器模块
公开(公告)号：US06721904B2
公开(公告)日：2004-04-13
申请号：US09907693
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： H02H305
CPC分类号： G11C29/12015 , G11C29/48 , G11C29/56012
摘要： The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.
摘要翻译：本发明涉及一种用于测试快速集成数字电路，特别是半导体模块（例如SDRAM）的系统。为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度，同时大规模生产所需的测试系统的高度并行性，将额外的半导体电路模块（BOST模块）插入到信号中标准测试设备和要测试的SDRAM之间的路径。该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率，并且根据测试信号来确定用于测试SDRAM模块的控制信号，地址和数据背景的信号序列设备以及在测试前编程的寄存器内容，在BOST模块中。

6. 发明授权

US07117403B2 Method and device for generating digital signal patterns 有权
公开(公告)号：US07117403B2
公开(公告)日：2006-10-03
申请号：US09907777
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/00 , G06F11/00 , G01R31/28
CPC分类号： G11C29/10 , G01R31/3183
摘要： The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

7. 发明授权

US06839397B2 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits 有权
标题翻译：用于产生用于测试高频同步数字电路的控制信号的电路配置
公开(公告)号：US06839397B2
公开(公告)日：2005-01-04
申请号：US09907784
申请日：2001-07-18
申请人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
发明人： Wolfgang Ernst , Gunnar Krause , Justus Kuhn , Jens Lüpke , Jochen Müller , Peter Pöchmüller , Michael Schittenhelm
IPC分类号： G11C29/14 , G06M3/00
CPC分类号： G11C29/14
摘要： A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.
摘要翻译：描述用于产生用于测试高频同步数字电路，特别是存储器芯片的控制信号的电路配置。以对应于要测试的数字电路的高时钟频率的时钟频率计时的p级移位寄存器连接到其并行加载输入p逻辑门，逻辑门逻辑地将静态控制字与动态n位置测试字。组合的逻辑值以低频加载时钟速率被加载到移位寄存器中，使得其值取决于在后者的时钟频率的每个时钟周期中加载到移位寄存器中的信息的控制信号在移位寄存器的串行输出。

8. 发明授权

US06762611B2 Test configuration and test method for testing a plurality of integrated circuits in parallel 失效
标题翻译：用于同时测试多个集成电路的测试配置和测试方法
公开(公告)号：US06762611B2
公开(公告)日：2004-07-13
申请号：US10010504
申请日：2001-12-05
申请人： Michael Hübner , Gunnar Krause , Justus Kuhn , Jochen Müller , Peter Pöchmüller , Jürgen Weidenhöfer
发明人： Michael Hübner , Gunnar Krause , Justus Kuhn , Jochen Müller , Peter Pöchmüller , Jürgen Weidenhöfer
IPC分类号： G01R1073
CPC分类号： G01R31/319 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G11C29/006 , G11C29/48
摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
摘要翻译：用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块。有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

9. 发明授权

US06396752B2 Method of testing a memory cell having a floating gate 有权
标题翻译：测试具有浮动栅极的存储单元的方法
公开(公告)号：US06396752B2
公开(公告)日：2002-05-28
申请号：US09771451
申请日：2001-01-26
申请人： Jens Lüpke , Peter Pöchmüller
发明人： Jens Lüpke , Peter Pöchmüller
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C16/04
摘要： The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.
摘要翻译：具有浮动栅极的存储单元通过向选择晶体管的源极或漏极施加电压冲击来测试。

10. 发明授权

US07466761B2 Configuration for the transmission of signals between a data processing device and a functional unit 有权
标题翻译：用于在数据处理设备和功能单元之间传输信号的配置
公开(公告)号：US07466761B2
公开(公告)日：2008-12-16
申请号：US10292844
申请日：2002-11-12
申请人： Peter Pöchmüller
发明人： Peter Pöchmüller
IPC分类号： H04L27/04
CPC分类号： G06F13/4018 , G06F13/405
摘要： A configuration for the transmission of signals includes a data processing device and a functional unit, which are connected to a first and second bus system, respectively, for the respective transmission of signals with different frequencies. A transmission unit is connected to the data processing device through the first bus system and to the functional unit through the second bus system, for the transmission and conversion of signals between the data processing device and the functional unit. It additionally serves for the electrical decoupling of the first bus system and the second bus system. As a result, independently of the electrical properties of the functional unit, a high data throughput is made possible in conjunction with still good detectability of the signals to be transmitted.
摘要翻译：用于信号传输的配置包括分别连接到第一和第二总线系统的数据处理设备和功能单元，用于各个具有不同频率的信号的传输。传输单元通过第一总线系统连接到数据处理设备，并通过第二总线系统连接到功能单元，用于数据处理设备和功能单元之间的信号传输和转换。它还用于第一总线系统和第二总线系统的电去耦。结果，独立于功能单元的电气特性，可以将高数据吞吐量与待传输信号的可靠性良好相结合。

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