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1. 发明授权

US08521992B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
标题翻译：在无序微处理器中预测和避免操作与存储比较的危害
公开(公告)号：US08521992B2
公开(公告)日：2013-08-27
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

2. 发明申请

US20110153986A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
标题翻译：预期和避免操作不合格的微处理器中的操作和比较危害
公开(公告)号：US20110153986A1
公开(公告)日：2011-06-23
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

3. 发明申请

US20110154116A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
公开(公告)号：US20110154116A1
公开(公告)日：2011-06-23
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F11/07
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

4. 发明授权

US08468325B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

5. 发明授权

US09135005B2 History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties 有权
标题翻译：用于存储用于优化操作数存储的多个指令的基于历史和对齐的破解比较处罚
公开(公告)号：US09135005B2
公开(公告)日：2015-09-15
申请号：US12695687
申请日：2010-01-28
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

6. 发明申请

US20110185158A1 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES 有权
标题翻译：用于存储多项指令的历史和对齐基础打破优化操作存储比较罚款
公开(公告)号：US20110185158A1
公开(公告)日：2011-07-28
申请号：US12695687
申请日：2010-01-28
申请人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F9/40
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

7. 发明授权

US08645669B2 Cracking destructively overlapping operands in variable length instructions 有权
标题翻译：以可变长度指令破坏性地重叠操作数
公开(公告)号：US08645669B2
公开(公告)日：2014-02-04
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第一组Uops用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

8. 发明申请

US20110276764A1 CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS 有权
标题翻译：在可变长度指令中打破破坏性重复操作
公开(公告)号：US20110276764A1
公开(公告)日：2011-11-10
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30 , G06F12/08 , G06F9/312
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第二组Uop用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

9. 发明授权

US09104399B2 Dual issuing of complex instruction set instructions 有权
标题翻译：双重发出复杂的指令集指令
公开(公告)号：US09104399B2
公开(公告)日：2015-08-11
申请号：US12645716
申请日：2009-12-23
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译：一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。指令发布单元向第一执行单元发出第一微操作以产生中间数据。然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。在延迟之后，向第二执行单元发出第二个微操作。

10. 发明授权

US08495341B2 Instruction length based cracking for instruction of variable length storage operands 有权
标题翻译：指令长度为可变长度存储操作数指令的破解
公开(公告)号：US08495341B2
公开(公告)日：2013-07-23
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

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