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1. 发明授权

US09135005B2 History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties 有权
标题翻译：用于存储用于优化操作数存储的多个指令的基于历史和对齐的破解比较处罚
公开(公告)号：US09135005B2
公开(公告)日：2015-09-15
申请号：US12695687
申请日：2010-01-28
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

2. 发明申请

US20110185158A1 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES 有权
标题翻译：用于存储多项指令的历史和对齐基础打破优化操作存储比较罚款
公开(公告)号：US20110185158A1
公开(公告)日：2011-07-28
申请号：US12695687
申请日：2010-01-28
申请人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F9/40
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

3. 发明授权

US08645669B2 Cracking destructively overlapping operands in variable length instructions 有权
标题翻译：以可变长度指令破坏性地重叠操作数
公开(公告)号：US08645669B2
公开(公告)日：2014-02-04
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第一组Uops用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

4. 发明申请

US20110276764A1 CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS 有权
标题翻译：在可变长度指令中打破破坏性重复操作
公开(公告)号：US20110276764A1
公开(公告)日：2011-11-10
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30 , G06F12/08 , G06F9/312
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第二组Uop用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

5. 发明申请

US20110202747A1 INSTRUCTION LENGTH BASED CRACKING FOR INSTRUCTION OF VARIABLE LENGTH STORAGE OPERANDS 有权
标题翻译：指定长度的破碎用于指示可变长度存储操作
公开(公告)号：US20110202747A1
公开(公告)日：2011-08-18
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30 , G06F9/40 , G06F9/312
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

6. 发明授权

US08495341B2 Instruction length based cracking for instruction of variable length storage operands 有权
标题翻译：指令长度为可变长度存储操作数指令的破解
公开(公告)号：US08495341B2
公开(公告)日：2013-07-23
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

7. 发明授权

US08464030B2 Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits 有权
标题翻译：基于指令字段，索引字段，操作数字段和各种其他指令文本位的指令破解和问题缩短
公开(公告)号：US08464030B2
公开(公告)日：2013-06-11
申请号：US12757330
申请日：2010-04-09
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Bruce Giamei , David Hutton
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Bruce Giamei , David Hutton
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/30032 , G06F9/30054 , G06F9/30058
摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。至少接收一条指令。至少对指令进行分析。识别与该至少一条指令相关联的指令类型。分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。然后执行一组操作单元。

8. 发明授权

US08938605B2 Instruction cracking based on machine state 有权
标题翻译：基于机器状态的指令开裂
公开(公告)号：US08938605B2
公开(公告)日：2015-01-20
申请号：US12718685
申请日：2010-03-05
申请人： Fadi Busaba , Bruce Giamei , David Hutton , Eric Schwarz
发明人： Fadi Busaba , Bruce Giamei , David Hutton , Eric Schwarz
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/342 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30189
摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.
摘要翻译：一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。至少接收一条指令。至少一条指令被解码。响应于解码确定当前机器状态。基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。执行一组操作单元。

9. 发明申请

US20050216713A1 Instruction text controlled selectively stated branches for prediction via a branch target buffer 审中-公开
标题翻译：指令文本通过分支目标缓冲器选择性地指定用于预测的分支
公开(公告)号：US20050216713A1
公开(公告)日：2005-09-29
申请号：US10809749
申请日：2004-03-25
申请人： Brian Prasky , Mark Check , Bruce Giamei , Timothy Slegel
发明人： Brian Prasky , Mark Check , Bruce Giamei , Timothy Slegel
IPC分类号： G06F9/00 , G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30181 , G06F9/3806
摘要： Disclosed is a method and apparatus providing the capability to prevent particular branches from being written into the BTB, thereby making them non-predictable. By making certain branches only detectable at decode time frame, branch prediction can completely run asynchronous of decode. By allowing branch prediction logic to cover as wide a range of branches as possible, the efficiency of fetching of branch targets way before the branch itself achieves a higher level of precision. This increased level of precision eliminates pipeline stalls between branches and targets where prior concerns of creating data integrity within the pipeline of a microprocessor existed.
摘要翻译：公开了提供防止特定分支被写入BTB的能力的方法和装置，从而使它们不可预测。通过使某些分支仅在解码时间帧可检测到，分支预测可以完全执行解码的异步。通过允许分支预测逻辑覆盖尽可能广泛的分支范围，在分支本身实现更高精度之前，提取分支目标的效率。这种增加的精度水平消除了分支和目标之间的流水线停顿，其中在微处理器管线内存在创建数据完整性的事先担心。

10. 发明授权

US5903479A Method and system for executing denormalized numbers 失效
标题翻译：执行非正规化数字的方法和系统
公开(公告)号：US5903479A
公开(公告)日：1999-05-11
申请号：US922191
申请日：1997-09-02
申请人： Eric Mark Schwarz , Bruce Giamei , Christopher A. Krygowski , Mark Anthony Check , John Stephen Liptay
发明人： Eric Mark Schwarz , Bruce Giamei , Christopher A. Krygowski , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F5/01 , G06F9/38
CPC分类号： G06F5/012 , G06F9/3861 , G06F9/3875 , G06F2207/3884
摘要： A method and system for processing instructions in a floating point unit for executing denormalized numbers in floating point pipeline via serializing uses an instruction unit and having a control unit and a pipelined data flow unit, a shifter and a rounding unit. The floating point unit has an external feedback path for providing intermediate result data from said rounding unit to an input of the pipelined data flow unit to reuse the pipeline for denormalization by passing intermediate results in the pipeline which have a denormalized condition computed after the exponent calculation of the shifting circuit directly from the rounding unit to the top of the dataflow in the pipeline via an external feedback path. The pipelined has two paths which are selected based on the presence of other instructions in the pipeline. If no other instructions are in the pipeline a first path is taken which uses the external feedback path from the rounding unit back into the top of the dataflow. When there are instructions in the pipeline a shifter unit performing normalization of the fraction indicates possible underflow of the exponent, and prepares to hold the exponent and the fraction in a floating point data flow register; and upon detection of exponent underflow during the rounder stage and detection of any other instructions in pipeline; then the control unit forces an interrupt for serialization, and cancels execution of this instruction and other instructions in pipeline.
摘要翻译：用于处理浮点单元中的指令的方法和系统，用于通过串行化来执行浮点流水线中的非正规化数字，使用指令单元并具有控制单元和流水线数据流单元，移位器和舍入单元。浮点单元具有用于将来自所述舍入单元的中间结果数据提供给流水线数据流单元的输入的外部反馈路径，以通过将具有在指数计算之后计算的非归一化状态的流水线中的中间结果重新使用来进行非规范化的移位电路通过外部反馈路径直接从舍入单元到流水线中的数据流的顶部。流水线有两个路径，这些路径是根据流水线中其他指令的存在而选择的。如果没有其他指令在流水线中，则采用第一路径，其使用从舍入单元返回到数据流的顶部的外部反馈路径。当在流水线中存在指令时，执行分数的归一化的移位单元指示指数的可能下溢，并准备将指数和分数保持在浮点数据流寄存器中; 并且在更整理阶段检测到指数下溢并检测管道中的任何其他指令; 那么控制单元强制中断进行串行化，并取消执行该指令和其他指令。

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