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1. 发明授权

US08188774B1 Apparatus and methods for activation of an interface on an integrated circuit 有权
标题翻译：用于激活集成电路上的接口的装置和方法
公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译：一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。收发器通道的偏移校准由物理介质连接电路执行。传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。随后，当集成电路的核心部件变得可操作时，该接口被激活。另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。还公开了其它实施例，方面和特征。

2. 发明授权

US06842034B1 Selectable dynamic reconfiguration of programmable embedded IP 有权
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US06842034B1
公开(公告)日：2005-01-11
申请号：US10612253
申请日：2003-07-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

3. 发明授权

US07443922B1 Circuitry for padded communication protocols 有权
标题翻译：用于填充通信协议的电路
公开(公告)号：US07443922B1
公开(公告)日：2008-10-28
申请号：US10714069
申请日：2003-11-14
申请人： Ramanand Venkata , Binh Ton
发明人： Ramanand Venkata , Binh Ton
IPC分类号： H04L27/00
CPC分类号： H04L25/4908 , H04J3/0605 , H04J3/062 , H04J3/0685 , H04J3/07 , H04L1/0064
摘要： Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.
摘要翻译：用于64b / 66b编码或其他类似填充数据信令的发射机和接收机电路。通过使用一个时钟信号源作为在填充之前和之后至少部分地处理数据的基础来简化所需的发射机时钟电路。采用适当的倍频和除数因子使其成为可能。在接收机电路中使用类似的技术。

4. 发明授权

US07268582B1 DPRIO for embedded hard IP 有权
标题翻译： DPRIO用于嵌入式硬IP
公开(公告)号：US07268582B1
公开(公告)日：2007-09-11
申请号：US11286038
申请日：2005-11-22
申请人： Michael M Zheng , Binh Ton , Chong H Lee
发明人： Michael M Zheng , Binh Ton , Chong H Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17732
摘要： An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.
摘要翻译：用于配置嵌入在FPGA中的硬IP的I / O接口包括寄存器加载信号，CSR初始化信号和寄存器数据信号。在编程DPRIO寄存器之后，寄存器数据控制硬IP块的操作。该接口支持CSR负载模式和MDIO接口。用户友好的I / O接口消除了对最终用户的所有要求，对最终用户实际上是透明的。

5. 发明授权

US08923440B1 Circuitry for padded communication protocols 有权
标题翻译：用于填充通信协议的电路
公开(公告)号：US08923440B1
公开(公告)日：2014-12-30
申请号：US12284191
申请日：2008-09-19
申请人： Ramanand Venkata , Binh Ton
发明人： Ramanand Venkata , Binh Ton
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/4908 , H04J3/0605 , H04J3/062 , H04J3/0685 , H04J3/07 , H04L1/0064
摘要： Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.
摘要翻译：用于64b / 66b编码或其他类似填充数据信令的发射机和接收机电路。通过使用一个时钟信号源作为在填充之前和之后至少部分地处理数据的基础来简化所需的发送器时钟电路。采用适当的倍频和除数因子使其成为可能。在接收机电路中使用类似的技术。

6. 发明授权

US07724598B1 Megafunction block and interface 有权
标题翻译：宏功能块和接口
公开(公告)号：US07724598B1
公开(公告)日：2010-05-25
申请号：US11737654
申请日：2007-04-19
申请人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
发明人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
IPC分类号： G11C7/00
CPC分类号： G06F12/0292 , G06F12/0623 , G06F2212/1048
摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.
摘要翻译：提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

7. 发明授权

US07071726B1 Selectable dynamic reconfiguration of programmable embedded IP 失效
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US07071726B1
公开(公告)日：2006-07-04
申请号：US11005390
申请日：2004-12-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

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