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1. 发明授权

US07724598B1 Megafunction block and interface 有权
标题翻译：宏功能块和接口
公开(公告)号：US07724598B1
公开(公告)日：2010-05-25
申请号：US11737654
申请日：2007-04-19
申请人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
发明人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
IPC分类号： G11C7/00
CPC分类号： G06F12/0292 , G06F12/0623 , G06F2212/1048
摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.
摘要翻译：提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

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