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1. 发明授权

US08188774B1 Apparatus and methods for activation of an interface on an integrated circuit 有权
标题翻译：用于激活集成电路上的接口的装置和方法
公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译：一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。收发器通道的偏移校准由物理介质连接电路执行。传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。随后，当集成电路的核心部件变得可操作时，该接口被激活。另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。还公开了其它实施例，方面和特征。

2. 发明申请

US20090161738A1 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US20090161738A1
公开(公告)日：2009-06-25
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

3. 发明授权

US09559881B2 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38 , H04L25/14
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

4. 发明授权

US08127215B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US08127215B2
公开(公告)日：2012-02-28
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

5. 发明授权

US08464088B1 Multiple channel bonding in a high speed clock network 有权
标题翻译：在高速时钟网络中进行多信道绑定
公开(公告)号：US08464088B1
公开(公告)日：2013-06-11
申请号：US12915794
申请日：2010-10-29
申请人： Toan Thanh Nguyen , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Thungoc M. Tran
发明人： Toan Thanh Nguyen , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Thungoc M. Tran
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/10
摘要： Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.
摘要翻译：公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。在本公开中更全面地描述了这些和其它实施例。

6. 发明授权

US07996749B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US07996749B2
公开(公告)日：2011-08-09
申请号：US11773234
申请日：2007-07-03
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

7. 发明申请

US20110235756A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20110235756A1
公开(公告)日：2011-09-29
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L27/06
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

8. 发明授权

US07759972B1 Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
标题翻译：具有异构高速串行接口电路的集成电路架构
公开(公告)号：US07759972B1
公开(公告)日：2010-07-20
申请号：US11981934
申请日：2007-10-31
申请人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。这些传统块离开设备的至少一个角落，不被这种遗留电路占用。这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

9. 发明授权

US08416001B2 Techniques for reducing duty cycle distortion in periodic signals 有权
标题翻译：降低周期信号中占空比失真的技术
公开(公告)号：US08416001B2
公开(公告)日：2013-04-09
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

10. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

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