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1. 发明授权

US07383490B2 Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
标题翻译：使用多节点计算机故障隔离交换误差检测值的方法和装置
公开(公告)号：US07383490B2
公开(公告)日：2008-06-03
申请号：US11106069
申请日：2005-04-14
申请人： Gheorghe Almasi , Matthias Augustin Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Sarabjeet Singh , Burkhard D. Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Gheorghe Almasi , Matthias Augustin Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Sarabjeet Singh , Burkhard D. Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1633
摘要： Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.
摘要翻译：方法和设备使用交换性错误检测值（例如，校验和）识别和隔离故障节点，在多个节点计算系统中执行故障隔离。当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值。每隔一段时间，与多节点计算机系统相关联的节点故障检测装置检索与节点相关联的交换错误检测值并将其存储在存储器中。当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值并将其存储在存储器中。节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。值的差异表示可能的故障节点。

2. 发明申请

US20060248370A1 Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
标题翻译：使用多节点计算机故障隔离交换误差检测值的方法和装置
公开(公告)号：US20060248370A1
公开(公告)日：2006-11-02
申请号：US11106069
申请日：2005-04-14
申请人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F11/00
CPC分类号： G06F11/1633
摘要： The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.
摘要翻译：本发明涉及在多节点计算系统中使用交换性错误检测值（例如校验和）识别和隔离故障节点来执行故障隔离的方法和装置。在本发明中，形成多节点计算系统的节点被联网在一起，并且在程序执行期间通过网络传送信息彼此通信。当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。间歇地，与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值，并将其存储在存储器中。当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。交换性错误检测值的差异表明节点可能有故障。

3. 发明申请

US20080307121A1 Direct Memory Access Transfer Completion Notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US20080307121A1
公开(公告)日：2008-12-11
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

4. 发明授权

US07765337B2 Direct memory access transfer completion notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US07765337B2
公开(公告)日：2010-07-27
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

5. 发明申请

US20070204112A1 LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
标题翻译：低延迟存储器访问和同步
公开(公告)号：US20070204112A1
公开(公告)日：2007-08-30
申请号：US11617276
申请日：2006-12-28
申请人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/52 , G06F2212/6028
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单预取。重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测算法。这使得硬件能够有效地预取不连续但重复的存储器访问模式。

6. 发明授权

US08756350B2 Method and apparatus for efficiently tracking queue entries relative to a timestamp 失效
标题翻译：相对于时间戳有效跟踪队列条目的方法和装置
公开(公告)号：US08756350B2
公开(公告)日：2014-06-17
申请号：US11768800
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F12/0835 , G06F12/0831
摘要： An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.
摘要翻译：一种用于跟踪在多处理器系统中发送的相干事件信号的装置和方法。该装置包括相干逻辑单元，每个单元具有多个队列结构，每个队列结构与在系统中传输的事件信号的相应发送者相关联。与队列结构相关联的定时电路控制接收的相干事件信号的排队和出队，并且计数器跟踪队列结构中剩余入队的多个相干事件信号，并且从接收到时间戳信号起出队。计数器机构产生一个输出信号，指示在接收时间戳信号时存在于队列结构中的所有相干事件信号已经出队。在一个实施例中，时间戳信号在存储器同步操作的开始被断言，并且输出信号指示当时间戳信号被断言时存在的所有相干事件已经完成。然后可以将该信号用作存储器同步操作的完成条件的一部分。

7. 发明申请

US20090006546A1 MULTIPLE NODE REMOTE MESSAGING 有权
标题翻译：多个节点远程消息传递
公开(公告)号：US20090006546A1
公开(公告)日：2009-01-01
申请号：US11768784
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send at least one remote message. The method includes various steps including controlling a DMA engine at first compute node (A) to prepare the single remote message to include a first message descriptor and at least one remote message descriptor for controlling the remote second compute node (B) to send at least one remote message, including putting the first message descriptor into an injection FIFO at the first compute node (A) and sending the single remote message and the at least one remote message descriptor to the second compute node (B).
摘要翻译：在形成为互连的计算节点的网络的并行计算机系统中传递远程消息的方法包括：第一计算节点（A）将单个远程消息发送到远程第二计算节点（B），以便控制远程第二计算节点（B）发送至少一个远程消息。该方法包括各种步骤，包括在第一计算节点（A）处控制DMA引擎以准备单个远程消息以包括第一消息描述符和至少一个远程消息描述符，用于控制远程第二计算节点（B）至少发送一个远程消息，包括将第一消息描述符放在第一计算节点（A）的注入FIFO中，并将单个远程消息和至少一个远程消息描述符发送到第二计算节点（B）。

8. 发明申请

US20090006672A1 METHOD AND APPARATUS FOR EFFICIENTLY TRACKING QUEUE ENTRIES RELATIVE TO A TIMESTAMP 失效
标题翻译：有效跟踪与TIMESTAMP相关的队列的方法和设备
公开(公告)号：US20090006672A1
公开(公告)日：2009-01-01
申请号：US11768800
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F3/00 , G06F1/04
CPC分类号： G06F12/0835 , G06F12/0831
摘要： An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.
摘要翻译：一种用于跟踪在多处理器系统中发送的相干事件信号的装置和方法。该装置包括相干逻辑单元，每个单元具有多个队列结构，每个队列结构与在系统中传输的事件信号的相应发送者相关联。与队列结构相关联的定时电路控制接收的相干事件信号的排队和出队，并且计数器跟踪队列结构中剩余入队的多个相干事件信号，并且从接收到时间戳信号起出队。计数器机构产生一个输出信号，指示在接收时间戳信号时存在于队列结构中的所有相干事件信号已经出队。在一个实施例中，时间戳信号在存储器同步操作的开始被断言，并且输出信号指示当时间戳信号被断言时存在的所有相干事件已经完成。然后可以将该信号用作存储器同步操作的完成条件的一部分。

9. 发明申请

US20090006296A1 DMA ENGINE FOR REPEATING COMMUNICATION PATTERNS 失效
标题翻译： DMA引擎重复通信模式
公开(公告)号：US20090006296A1
公开(公告)日：2009-01-01
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F15/18
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

10. 发明授权

US07788334B2 Multiple node remote messaging 有权
标题翻译：多节点远程消息传递
公开(公告)号：US07788334B2
公开(公告)日：2010-08-31
申请号：US11768784
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F15/167 , G06F13/28
CPC分类号： G06F15/16
摘要： A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send at least one remote message. The method includes various steps including controlling a DMA engine at first compute node (A) to prepare the single remote message to include a first message descriptor and at least one remote message descriptor for controlling the remote second compute node (B) to send at least one remote message, including putting the first message descriptor into an injection FIFO at the first compute node (A) and sending the single remote message and the at least one remote message descriptor to the second compute node (B).
摘要翻译：在形成为互连的计算节点的网络的并行计算机系统中传递远程消息的方法包括：第一计算节点（A）将单个远程消息发送到远程第二计算节点（B），以便控制远程第二计算节点（B）发送至少一个远程消息。该方法包括各种步骤，包括在第一计算节点（A）处控制DMA引擎以准备单个远程消息以包括第一消息描述符和至少一个远程消息描述符，用于控制远程第二计算节点（B）至少发送一个远程消息，包括将第一消息描述符放在第一计算节点（A）的注入FIFO中，并将单个远程消息和至少一个远程消息描述符发送到第二计算节点（B）。

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