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1. 发明授权

US6110792A Method for making DRAM capacitor strap 有权
标题翻译：制造DRAM电容带的方法
公开(公告)号：US6110792A
公开(公告)日：2000-08-29
申请号：US136604
申请日：1998-08-19
申请人： Gary B. Bronner , Carl J. Radens , Juergen Wittmann
发明人： Gary B. Bronner , Carl J. Radens , Juergen Wittmann
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/10 , H01L21/20
CPC分类号： H01L27/10861
摘要： A method of forming a trench capacitor comprises steps of forming a trench in a substrate, partially filling the trench with a first conductive material, lining a portion of the trench above the first conductive material with a collar material, etching the collar material to a strap depth below a top of the trench, and filling the trench with a second conductive material, wherein a portion of the second conductive material positioned between the strap depth and the top of the trench comprises a buried strap.
摘要翻译：一种形成沟槽电容器的方法包括以下步骤：在衬底中形成沟槽，用第一导电材料部分地填充沟槽，用第一导电材料的一部分沟槽材料衬套沟槽的一部分，将衬套材料蚀刻到带深度在沟槽的顶部之下，并且用第二导电材料填充沟槽，其中位于带深度和沟槽顶部之间的第二导电材料的一部分包括埋设带。

2. 发明授权

US07009237B2 Out of the box vertical transistor for eDRAM on SOI 有权
标题翻译：在SOI上用于eDRAM的开箱式垂直晶体管
公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

3. 发明授权

US06566177B1 Silicon-on-insulator vertical array device trench capacitor DRAM 有权
标题翻译：绝缘体上的垂直阵列器件沟槽电容器DRAM
公开(公告)号：US06566177B1
公开(公告)日：2003-05-20
申请号：US09427257
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L2100
CPC分类号： H01L27/10864 , H01L27/1087
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.
摘要翻译：一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。掩埋氧化层将SOI层与硅衬底隔离。沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。最初，在晶圆中形成掩埋氧化物层。深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。在沟槽中形成保护侧壁。然后，将深沟槽蚀刻到衬底中。衬底中的体积被扩大以形成瓶形沟槽。在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。浅沟槽隔离（STI）用于隔离和定义细胞。在晶片上形成位线和字线。

4. 发明授权

US06429474B1 Storage-capacitor electrode and interconnect 失效
标题翻译：储存电容电极和互连
公开(公告)号：US06429474B1
公开(公告)日：2002-08-06
申请号：US09547335
申请日：2000-04-11
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

5. 发明授权

US06426252B1 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap 失效
标题翻译：绝缘体上的垂直阵列DRAM单元，具有自对准埋地带
公开(公告)号：US06426252B1
公开(公告)日：2002-07-30
申请号：US09427256
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/1203
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.
摘要翻译：绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。在SOI层的BOX层中形成凹部。凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。将掺杂剂注入到晶片中以限定器件区域。存取晶体管栅极沿SOI层侧壁形成。形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。形成字词和位线以完成内存数组。

6. 发明授权

US06395594B2 Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US06395594B2
公开(公告)日：2002-05-28
申请号：US09750790
申请日：2001-01-02
申请人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
发明人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10882 , H01L27/10894
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括用于制造两种类型互连的至少一个并且优选两个电容器电极。制造DRAM存储单元的方法包括：形成一个或多个电容电极，同时形成存储单元的存储电容器的电极，以及与辅助电容器电极相同的材料。

7. 发明授权

US06265308B1 Slotted damascene lines for low resistive wiring lines for integrated circuit 有权
标题翻译：用于集成电路的低电阻布线的开槽镶嵌线
公开(公告)号：US06265308B1
公开(公告)日：2001-07-24
申请号：US09201205
申请日：1998-11-30
申请人： Gary B. Bronner , Greg Costrini , Carl J. Radens , Rainer F. Schnabel
发明人： Gary B. Bronner , Greg Costrini , Carl J. Radens , Rainer F. Schnabel
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A process of forming a wiring in a semiconductor interlayer dielectric, include simultaneously patterning a via and a slotted line in the interlayer diectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal.
摘要翻译：在半导体层间电介质中形成布线的工艺包括同时对夹层中的通孔和开槽线进行图案化，同时蚀刻通孔和开槽线，同时用金属填充通孔和开槽线。

8. 发明授权

US06808981B2 Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
标题翻译：用于制造具有双门控垂直MOSFET和自对准STI的6F2沟槽DRAM单元的方法
公开(公告)号：US06808981B2
公开(公告)日：2004-10-26
申请号：US10375654
申请日：2003-02-27
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译：提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与单元的字线和位线自对准的区域）的存储单元。本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。还提供了制造本发明的存储单元的方法。

9. 发明授权

US06570208B2 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
标题翻译： 6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI
公开(公告)号：US06570208B2
公开(公告)日：2003-05-27
申请号：US09766013
申请日：2001-01-18
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译：提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。还提供了制造本发明的存储单元的方法。

10. 发明授权

US06501117B1 Static self-refreshing DRAM structure and operating mode 失效
标题翻译：静态自刷新DRAM结构和工作模式
公开(公告)号：US06501117B1
公开(公告)日：2002-12-31
申请号：US10007846
申请日：2001-11-05
申请人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/11 , G11C11/404 , H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.
摘要翻译：在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。在凹陷节点电介质层上方，带区域空间填充有埋地导体。在DT上的节点电极和掩埋带上形成氧化物（TTO）层。在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。电池具有第一状态和相反的操作状态。形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

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