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1. 发明申请

US20110320665A1 Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：在多节点对称多处理计算机中管理并发序列化中断广播命令
公开(公告)号：US20110320665A1
公开(公告)日：2011-12-29
申请号：US12821752
申请日：2010-06-23
申请人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
发明人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译：在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。

2. 发明授权

US08375155B2 Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中管理并发序列化中断广播命令
公开(公告)号：US08375155B2
公开(公告)日：2013-02-12
申请号：US12821752
申请日：2010-06-23
申请人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
发明人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译：在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。

3. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

4. 发明授权

US5490261A Interlock for controlling processor ownership of pipelined data for a store in cache 失效
标题翻译：用于控制缓存中存储的流水线数据的处理器所有权的联锁
公开(公告)号：US5490261A
公开(公告)日：1996-02-06
申请号：US680176
申请日：1991-04-03
申请人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
发明人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.
摘要翻译：通过在流水线中的数据单元上提供所有权互锁到存储型缓存来保护进程所有权指示中的数据完整性。所有权互锁防止对高速缓存数据单元发生任何处理器所有权改变（即，独占或只读所有权），直到所有未完成的存储已经在高速缓存数据单元中进行，之后可以改变所有权。所有权变更可以通过交叉无效（XI）信号发送给处理器。在存储由处理器完成之后，流水线接收到未完成的存储，并且从流水线输出的未完成存储到存储缓存中。连续的商店流程被启用进出管道，以加快对高速缓存中数据单元所需的所有权的更改。连续流程避免了停止处理器将存储放入流水线中，并避免在指示处理器所有权的更改之前将所有未完成的存储从管道中强制进入高速缓存。

5. 发明申请

US20090006693A1 Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large SMP Computer System 有权
标题翻译：大型SMP计算机系统共享管道公平仲裁的装置与方法
公开(公告)号：US20090006693A1
公开(公告)日：2009-01-01
申请号：US11768934
申请日：2007-06-27
申请人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/14
CPC分类号： G06F13/14 , G06F9/50 , G06F2209/5021 , Y02D10/14 , Y02D10/22
摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.
摘要翻译：通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。

6. 发明申请

US20130339593A1 REDUCING PENALTIES FOR CACHE ACCESSING OPERATIONS 有权
标题翻译：减少高速缓存接入操作的处罚
公开(公告)号：US20130339593A1
公开(公告)日：2013-12-19
申请号：US13523523
申请日：2012-06-14
申请人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F9/3824 , G06F12/0846 , G06F12/0855 , Y02D10/13
摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.
摘要翻译：提供了用于减少高速缓存访问操作的惩罚的计算机程序产品。计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。

7. 发明申请

US20110320744A1 DIAGNOSTIC DATA COLLECTION AND STORAGE PUT-AWAY STATION IN A MULTIPROCESSOR SYSTEM 失效
标题翻译：多处理器系统中的诊断数据采集和存储插入站
公开(公告)号：US20110320744A1
公开(公告)日：2011-12-29
申请号：US12822704
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones
IPC分类号： G06F11/34 , G06F12/00
CPC分类号： G06F11/0778 , G06F11/0724 , G06F11/3636 , G06F11/3648 , G06F11/366
摘要： A computer-implemented method for collecting diagnostic data within a multiprocessor system that includes capturing diagnostic data via a plurality of collection points disposed at a source location within the multiprocessor system, routing the captured diagnostic data to a data collection station at the source location, providing a plurality of buffers within the data collection station, and temporarily storing the captured diagnostic data on at least one of the plurality of buffers, and transferring the captured diagnostic data to a target storage location on a same chip as the source location or another storage location on a same node.
摘要翻译：一种用于在多处理器系统内收集诊断数据的计算机实现的方法，其包括经由多处理器系统中的源位置处的多个收集点捕获诊断数据，将所捕获的诊断数据路由到源位置处的数据采集站，数据收集站内的多个缓冲器，并且将所捕获的诊断数据临时存储在多个缓冲器中的至少一个缓冲器上，并将捕获的诊断数据传送到与源位置或另一个存储位置相同的芯片上的目标存储位置在同一个节点上。

8. 发明申请

US20130339606A1 REDUCING STORE OPERATION BUSY TIMES 有权
标题翻译：减少存储操作繁忙时间
公开(公告)号：US20130339606A1
公开(公告)日：2013-12-19
申请号：US13523567
申请日：2012-06-14
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F9/38 , G06F9/3855 , G06F12/0855 , G11C7/22 , G11C2207/229 , Y02D10/13
摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.
摘要翻译：提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

9. 发明申请

US20110320731A1 ON DEMAND ALLOCATION OF CACHE BUFFER SLOTS 有权
标题翻译：关于缓存缓冲区的需求分配
公开(公告)号：US20110320731A1
公开(公告)日：2011-12-29
申请号：US12822398
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
IPC分类号： G06F12/08 , G06F13/00 , G06F3/00
CPC分类号： G06F12/0895 , G06F12/0871
摘要： Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.
摘要翻译：高速缓存缓存槽的动态分配包括接收执行需要存储缓冲器时隙的操作的请求，存储缓冲槽位于存储级别。高速缓存缓存槽的动态分配还包括确定请求指定的高速缓存索引的存储缓冲区的可用性。在确定存储缓冲器时隙不可用时，高速缓存缓冲器时隙的动态分配包括驱逐存储在存储缓冲器时隙中的数据，并且为与请求相关联的数据保留存储缓冲器时隙。

10. 发明授权

US09075727B2 Reducing penalties for cache accessing operations 有权
公开(公告)号：US09075727B2
公开(公告)日：2015-07-07
申请号：US13523523
申请日：2012-06-14
申请人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0864 , G06F9/3824 , G06F12/0846 , G06F12/0855 , Y02D10/13
摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

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