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1. 发明授权

US5490261A Interlock for controlling processor ownership of pipelined data for a store in cache 失效
标题翻译：用于控制缓存中存储的流水线数据的处理器所有权的联锁
公开(公告)号：US5490261A
公开(公告)日：1996-02-06
申请号：US680176
申请日：1991-04-03
申请人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
发明人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.
摘要翻译：通过在流水线中的数据单元上提供所有权互锁到存储型缓存来保护进程所有权指示中的数据完整性。所有权互锁防止对高速缓存数据单元发生任何处理器所有权改变（即，独占或只读所有权），直到所有未完成的存储已经在高速缓存数据单元中进行，之后可以改变所有权。所有权变更可以通过交叉无效（XI）信号发送给处理器。在存储由处理器完成之后，流水线接收到未完成的存储，并且从流水线输出的未完成存储到存储缓存中。连续的商店流程被启用进出管道，以加快对高速缓存中数据单元所需的所有权的更改。连续流程避免了停止处理器将存储放入流水线中，并避免在指示处理器所有权的更改之前将所有未完成的存储从管道中强制进入高速缓存。

2. 发明授权

US4142234A Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system 失效
标题翻译：偏置过滤器存储器，用于过滤多处理器系统中缓存目录的不必要询问
公开(公告)号：US4142234A
公开(公告)日：1979-02-27
申请号：US855485
申请日：1977-11-28
申请人： Bradford M. Bean , Keith N. Langston , Richard L. Partridge , Kian-Bon K. Sy
发明人： Bradford M. Bean , Keith N. Langston , Richard L. Partridge , Kian-Bon K. Sy
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00 , G06F15/16
CPC分类号： G06F12/0808
摘要： The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests.The filter memory may have one or more registers, or be an array. Invalidation interrogation addresses from each remote processor and from local and/or remote channels are received and compared against each valid address recorded in the filter memory. If they compare unequal, the received address is recorded in the filter memory as a valid address, and it is gated into BIAS to perform a cache interrogation. If equal, the inputted address is prevented from entering the filter memory or the BIAS, so that it cannot cause any cache interrogation. Deletion from the filter memory is done when the associated processor fetches a block of data into its cache. Deletion may be of all entries in the filter memory, or of only a valid entry having an address equal to the block fetch address in a fetch address register (FAR). Deletion may be done by resetting a valid bit with each entry.
摘要翻译：所公开的实施例滤除多处理器（MP）系统中的处理器的高速缓存目录的许多不必要的询问，由此减少与每个相关联的处理器的缓冲区无效地址堆栈（BIAS）的所需大小，并且通过允许它在机器周期期间访问其缓存，在先前的MP被要求无效询问。当每个通道或处理器向共享主存储器生成存储请求时，可以完成每个远程处理器高速缓存目录的无效询问。

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