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1. 发明授权

US06798255B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06798255B2
公开(公告)日：2004-09-28
申请号：US09931250
申请日：2001-08-17
申请人： Fumikazu Takahashi , Tatsumi Yamauchi , Fumio Murabayashi , Kazuhisa Miyamoto , Kazuharu Kuchimachi
发明人： Fumikazu Takahashi , Tatsumi Yamauchi , Fumio Murabayashi , Kazuhisa Miyamoto , Kazuharu Kuchimachi
IPC分类号： H03B2100
CPC分类号： H03K5/15013
摘要： A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.
摘要翻译：一种半导体集成电路装置，包括驱动电路，连接到驱动电路的第一长距离布线和连接在第一长距离布线的整个长度上的多个门电路，使得驱动电路的输出信号经由第一长距离布线由多个门电路接收，其中布置在连接到驱动电路的输入端的门电路的输入端附近的节点和第一长距离布线的端部通过第二长距离布线和增速电路连接。

2. 发明授权

US06539322B1 Sensor device 有权
标题翻译：传感器装置
公开(公告)号：US06539322B1
公开(公告)日：2003-03-25
申请号：US09583770
申请日：2000-05-31
申请人： Masahiro Matsumoto , Kohei Sakurai , Fumio Murabayashi , Hiromichi Yamada , Tatsumi Yamauchi , Atsushi Miyazaki , Keiji Hanzawa
发明人： Masahiro Matsumoto , Kohei Sakurai , Fumio Murabayashi , Hiromichi Yamada , Tatsumi Yamauchi , Atsushi Miyazaki , Keiji Hanzawa
IPC分类号： G06M1102
CPC分类号： G01D3/08 , G01D3/022 , Y10T436/11
摘要： A sensor device is provided which included a digital arithmetic processing unit which performs arithmetic processing through a program stored therein in advance, a pulse generator for generating pulses through the program, and a unit for causing the output voltage of the sensor device to stay at either a power source voltage concerned or the ground voltage, when the pulses from the pulse generator are interrupted, thereby, a sensor device using digital arithmetic processing and outputting analogue voltages is provided allowing the host system to judge easily whether the sensor device is operating normally or is failing.
摘要翻译：提供了一种传感器装置，其包括：数字运算处理单元，其预先通过存储在其中的程序执行算术处理;脉冲发生器，用于通过程序产生脉冲;以及单元，用于使传感器装置的输出电压停留在任一个当来自脉冲发生器的脉冲被中断时，提供有关的电源电压或接地电压，由此提供使用数字运算处理和输出模拟电压的传感器装置，允许主机系统容易地判断传感器装置是否正常运行，或者失败了

3. 发明授权

US5612640A Self-timed semiconductor integrated circuit device 失效
标题翻译：自定时半导体集成电路器件
公开(公告)号：US5612640A
公开(公告)日：1997-03-18
申请号：US308303
申请日：1994-09-19
申请人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
发明人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
IPC分类号： G06F7/00 , G06F9/38 , G06F15/78 , H04L7/00 , H03K5/13
CPC分类号： G06F9/3869
摘要： A semiconductor integrated circuit device is equipped with a series of data handling stages, at least one of which includes a plurality of functional blocks arranged in parallel, a connecting means for connecting the functional blocks to functional blocks in a subsequent data handling stage, and a detection means for detecting data flow along a first connection in the connecting means. The detection means is included within a control means which controls data flow through at least one other connection in the connecting means based on the detection of data flow through the first connection in the connecting means. In a second embodiment, the semiconductor integrated circuit device includes a plurality of functional blocks arranged in a series for handling data along the series, a connecting means for handling data flow between at least two of the functional blocks, a data detecting means for detecting data flow along a selected connection in the connecting means, and for controlling data flow along another connection in the connecting means based on the detection of data flow through the selected connection.
摘要翻译：半导体集成电路器件配备有一系列数据处理级，其中至少一个包括并行布置的多个功能块，用于在后续数据处理阶段将功能块连接到功能块的连接装置，以及检测装置，用于沿连接装置中的第一连接检测数据流。检测装置包括在控制装置内，该控制装置基于通过连接装置中的第一连接的数据流的检测来控制连接装置中的至少一个其他连接的数据流。在第二实施例中，半导体集成电路器件包括一系列用于处理串联数据的功能块，用于处理至少两个功能块之间的数据流的连接装置，用于检测数据的数据检测装置沿着所述连接装置中的所选连接流动，并且用于基于通过所选择的连接的数据流的检测来控制沿连接装置中的另一连接的数据流。

4. 发明授权

US06713975B2 Lighting apparatus, lighting control system and home electric appliance 有权
标题翻译：照明设备，照明控制系统和家用电器
公开(公告)号：US06713975B2
公开(公告)日：2004-03-30
申请号：US09915365
申请日：2001-07-27
申请人： Tatsumi Yamauchi , Fumio Murabayashi , Haruki Komatsu , Akio Inada
发明人： Tatsumi Yamauchi , Fumio Murabayashi , Haruki Komatsu , Akio Inada
IPC分类号： G05F100
CPC分类号： H05B37/0254 , H05B37/0245 , Y02B20/40
摘要： A lighting apparatus capable of improving amenity and energy-saving and controlling a lighting load as a user intends to do. The lighting apparatus is connected to a network and controlling the lighting load corresponding to information from the network, and the lighting apparatus further comprises an automatic mode for controlling the lighting load corresponding to the information from the network, a manual mode for controlling the lighting load independently of the information from the network, and a switching means for switching between the automatic mode and the manual mode.
摘要翻译：一种照明装置，其能够改善舒适性和节能性并且控制用户打算做的照明负载。照明装置连接到网络并控制与来自网络的信息相对应的照明负载，并且照明装置还包括用于控制与来自网络的信息相对应的照明负载的自动模式，用于控制照明负载的手动模式独立于来自网络的信息，以及用于在自动模式和手动模式之间切换的切换装置。

5. 发明授权

US5684729A Floating-point addition/substraction processing apparatus and method thereof 失效
标题翻译：浮点加法/减法处理装置及其方法
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
IPC分类号： G06F7/50 , G06F7/74
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译：为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量，点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果，移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

6. 发明授权

US5677641A Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
标题翻译：门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统
公开(公告)号：US5677641A
公开(公告)日：1997-10-14
申请号：US423378
申请日：1995-04-18
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： G11C11/41 , H03K3/3565 , H03K19/0185 , H03K19/0948
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
摘要翻译：本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

7. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

8. 发明授权

US5931895A Floating-point arithmetic processing apparatus 失效
标题翻译：浮点算术处理装置
公开(公告)号：US5931895A
公开(公告)日：1999-08-03
申请号：US789430
申请日：1997-01-29
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
IPC分类号： G06F7/38 , G06F5/01 , G06F7/00 , G06F7/483 , G06F7/74 , G06F7/76 , G06F7/52
CPC分类号： G06F5/012 , G06F7/483
摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.
摘要翻译：一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

9. 发明授权

US5869990A Self-timed semiconductor integrated circuit device 失效
标题翻译：自定义半导体集成电路器件
公开(公告)号：US5869990A
公开(公告)日：1999-02-09
申请号：US792799
申请日：1997-02-03
申请人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
发明人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
IPC分类号： G06F7/00 , G06F9/38 , G06F15/78 , H04L7/00 , H03K5/13
CPC分类号： G06F9/3869
摘要： A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.
摘要翻译：提供一种半导体集成电路器件，其包括至少一个第一功能电路块，其接收输入信号并执行逻辑运算以输出输出信号。至少一个第二功能电路块与第一功能电路块并联连接。第二功能电路块还响应输入信号以执行逻辑运算并输出输出信号作为结果。第一和第二功能电路块彼此连接，使得第二功能电路块将与第一功能电路块同步操作。更具体地，第一功能电路块被布置成控制第二功能电路块的输出定时。

10. 发明授权

US06538866B1 Circuit for protecting a load from an overvoltage 失效
标题翻译：用于保护负载免受过电压的电路
公开(公告)号：US06538866B1
公开(公告)日：2003-03-25
申请号：US09526737
申请日：2000-03-16
申请人： Keiji Hanzawa , Masahiro Matsumoto , Fumio Murabayashi , Tatsumi Yamauchi , Hiromichi Yamada , Kohei Sakurai , Atsushi Miyazaki
发明人： Keiji Hanzawa , Masahiro Matsumoto , Fumio Murabayashi , Tatsumi Yamauchi , Hiromichi Yamada , Kohei Sakurai , Atsushi Miyazaki
IPC分类号： H02H900
CPC分类号： H01L27/0251 , H02H9/04
摘要： A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.
摘要翻译：可以通过MOS晶体管制造工艺将用于保护负载的过电压的电路与负载集成在同一芯片上。该过电压保护电路由浪涌保护电路，过电压检测电路和开关电路构成。包括两个MOS晶体管的浪涌保护电路工作，借助于两个MOS晶体管的源极 - 漏极击穿电压来钳位施加到电源接收端的浪涌电压，从而吸收浪涌能量。包括两个MOS晶体管的过电压检测电路进行工作，从而以两个MOS晶体管的源极 - 漏极电压作为参考电压来监视从浪涌保护电路提供的直流电压，从而检测过电压。过电压检测输出使开关电路的MOS晶体管成为关断状态，以保护负载。

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