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1. 发明授权

US5931895A Floating-point arithmetic processing apparatus 失效
标题翻译：浮点算术处理装置
公开(公告)号：US5931895A
公开(公告)日：1999-08-03
申请号：US789430
申请日：1997-01-29
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
IPC分类号： G06F7/38 , G06F5/01 , G06F7/00 , G06F7/483 , G06F7/74 , G06F7/76 , G06F7/52
CPC分类号： G06F5/012 , G06F7/483
摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.
摘要翻译：一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

2. 发明授权

US5684729A Floating-point addition/substraction processing apparatus and method thereof 失效
标题翻译：浮点加法/减法处理装置及其方法
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
IPC分类号： G06F7/50 , G06F7/74
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译：为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量，点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果，移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

3. 发明授权

US4780810A Data processor with associative memory storing vector elements for vector conversion 失效
标题翻译：具有相关存储器的数据处理器，用于存储向量转换的向量元素
公开(公告)号：US4780810A
公开(公告)日：1988-10-25
申请号：US737453
申请日：1985-05-24
申请人： Shunichi Torii , Keiji Kojima , Noriyasu Ido
发明人： Shunichi Torii , Keiji Kojima , Noriyasu Ido
IPC分类号： G11C15/04 , G06F15/78 , G06F17/16 , G06F17/30 , G06F15/347 , G06F5/00
CPC分类号： G06F15/8076 , G06F17/30949 , G06F17/30982
摘要： Associative keys and retrieve outputs corresponding thereto are registered to an associative memory in a vector data conversion apparatus. Conversion vector data stored in the main storage and comprising vector elements of the same type of an associative key is sequentially read out for each vector element and is inputted to a comparator, which then compares the vector element with the associative keys beforehand registered to the associative memory so as to determine whether or not a matching condition exists therebetween. When the comparator detects the matching condition, a retrieve output corresponding to the matched associative key is read out from the associative memory and is stored in the main storage. While the conversion vector data is sequentially read out for each vector in this manner, the retrieve output data is sequentially stored in the main storage so as to generate the converted vector data comprising the retrieve output data as vector elements. A user identifier may also be inputted as a compare element together with the associative key, thereby preventing an erroneous data conversion from taking place even when a plurality of users share the vector data conversion apparatus.
摘要翻译：相关键和检索对应的输出被登记到矢量数据转换装置中的关联存储器。存储在主存储器中并且包括相关类型的关联键的向量元素的转换矢量数据被顺序地读出用于每个向量元素，并且被输入到比较器，比较器将比较矢量元素与预先登记到关联关联的关联密钥存储器，以便确定它们之间是否存在匹配条件。当比较器检测到匹配条件时，从关联存储器读出对应于匹配关联密钥的检索输出，并存储在主存储器中。虽然以这种方式顺序地读取每个向量的转换向量数据，但是检索输出数据被顺序地存储在主存储器中，以便生成包括作为向量元素的检索输出数据的转换的向量数据。也可以将用户标识符与关联密钥一起作为比较元素输入，从而即使当多个用户共享向量数据转换装置时也防止错误的数据转换。

4. 发明授权

US4723206A Vector processor 失效
标题翻译：矢量处理器
公开(公告)号：US4723206A
公开(公告)日：1988-02-02
申请号：US737686
申请日：1985-05-24
申请人： Keiji Kojima , Shunichi Torii , Noriyasu Ido
发明人： Keiji Kojima , Shunichi Torii , Noriyasu Ido
IPC分类号： G06F7/04 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F15/8053
摘要： A vector to be processed consisting of a plurality of partial vectors each having a variable number of vector elements and a key vector consisting of a fixed number of vector elements are vector-processed while the vector elements of those vectors are sequentially read out. A vector processor has a punctuation detection circuit for detecting a punctuation between the partial vectors in the vector to be processed. The reading of the key vector is restored to the reading of the start vector element in accordance with the detection signal from the punctuation detection circuit.
摘要翻译：对由矢量进行矢量处理的矢量进行矢量处理，该矢量由具有可变数量的矢量元素的多个部分矢量和由固定数量的向量元素构成的关键矢量构成。矢量处理器具有用于检测待处理矢量中的部分矢量之间的标点符号的标点符号检测电路。根据来自标点符号检测电路的检测信号，将键向量的读取恢复为起始向量元素的读取。

5. 发明授权

US5572151A Pass transistor type selector circuit and digital logic circuit 失效
标题翻译：通过晶体管型选择电路和数字逻辑电路
公开(公告)号：US5572151A
公开(公告)日：1996-11-05
申请号：US511802
申请日：1995-08-07
申请人： Makoto Hanawa , Kenji Kaneko , Noriyasu Ido
发明人： Makoto Hanawa , Kenji Kaneko , Noriyasu Ido
IPC分类号： H03K19/20 , G06F7/50 , G06F7/509 , G06F7/60 , H03K17/693 , H03K19/0944 , H03K19/173
CPC分类号： G06F7/509 , G06F7/607 , H03K17/693 , H03K19/1737
摘要： A pass transistor type selector circuit comprises a control signal supplying circuit for supplying a pair of control signals of opposite phases to the respective gate electrodes of a pair of nMOS transistors of a selecting circuit. The control signal supplying circuit includes a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal is low level. The control signal interrupting means is provided with a discharging means for discharging high-level one of the gate electrodes of the nMOS transistors of the signal selecting circuit while the clock signal is low level. The discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of the signal selecting circuit and a grounding terminal.
摘要翻译：传输晶体管型选择器电路包括控制信号提供电路，用于将一对相反相位的控制信号提供给选择电路的一对nMOS晶体管的各个栅电极。控制信号提供电路包括与时钟信号同步工作的控制信号中断装置，以便在时钟信号为低电平时有选择地中断向信号选择电路提供控制信号。控制信号中断装置设置有用于在时钟信号为低电平时对信号选择电路的nMOS晶体管的高电平一个栅电极进行放电的放电装置。放电装置包括两个nMOS晶体管，每个晶体管连接在信号选择电路的nMOS晶体管的各个栅电极和接地端子之间。

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