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1. 发明授权

US5677641A Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
标题翻译：门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统
公开(公告)号：US5677641A
公开(公告)日：1997-10-14
申请号：US423378
申请日：1995-04-18
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： G11C11/41 , H03K3/3565 , H03K19/0185 , H03K19/0948
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
摘要翻译：本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

2. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

3. 发明授权

US06462580B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
标题翻译：门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统
公开(公告)号：US06462580B2
公开(公告)日：2002-10-08
申请号：US09749474
申请日：2000-12-28
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
摘要翻译：本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低振幅以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流，尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

4. 发明授权

US06172532B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06172532B2
公开(公告)日：2001-01-09
申请号：US08925428
申请日：1997-09-08
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K190948
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

5. 发明授权

US07193929B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07193929B2
公开(公告)日：2007-03-20
申请号：US11446219
申请日：2006-06-05
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： G11C8/18
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译：半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与外部时钟信号的频率。内部时钟信号用于内部电路的同步操作。即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部晶体振荡器的附件和外部时钟信号的输入。

6. 发明申请

US20080309383A1 Semiconductor Integrated Circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20080309383A1
公开(公告)日：2008-12-18
申请号：US12107069
申请日：2008-04-21
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译：半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与外部时钟信号的频率。内部时钟信号用于内部电路的同步操作。即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部晶体振荡器的附件和外部时钟信号的输入。

7. 发明授权

US07382681B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07382681B2
公开(公告)日：2008-06-03
申请号：US11708346
申请日：2007-02-21
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译：半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与外部时钟信号的频率。内部时钟信号用于内部电路的同步操作。即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部晶体振荡器的附件和外部时钟信号的输入。

8. 发明申请

US20060227650A1 Semiconductor integrated circuit 有权
公开(公告)号：US20060227650A1
公开(公告)日：2006-10-12
申请号：US11446217
申请日：2006-06-05
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

9. 发明授权

US07061825B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07061825B2
公开(公告)日：2006-06-13
申请号：US10867013
申请日：2004-06-15
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译：半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与外部时钟信号的频率。内部时钟信号用于内部电路的同步操作。即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部晶体振荡器的附件和外部时钟信号的输入。

10. 发明申请

US20050047265A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050047265A1
公开(公告)日：2005-03-03
申请号：US10867013
申请日：2004-06-15
申请人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
发明人： Naoki Yada , Yasuyuki Saito , Yasushi Shibatsuka , Katsunori Koike , Mitsuhiko Okutsu
IPC分类号： G06F1/12 , G06F1/04 , G06F1/08 , G11C7/22 , G11C8/00 , H03K3/03 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/08
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译：半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与外部时钟信号的频率。内部时钟信号用于内部电路的同步操作。即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部晶体振荡器的附件和外部时钟信号的输入。

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