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1. 发明授权

US07446014B2 Nanoelectrochemical cell 失效
公开(公告)号：US07446014B2
公开(公告)日：2008-11-04
申请号：US11580623
申请日：2006-10-12
申请人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
发明人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01G9/07 , Y10S977/762 , Y10T29/417
摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

2. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

3. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

4. 发明申请

US20080096345A1 Nanoelectrochemical cell 失效
标题翻译：纳米电化学电池
公开(公告)号：US20080096345A1
公开(公告)日：2008-04-24
申请号：US11580623
申请日：2006-10-12
申请人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
发明人： Fengyan Zhang , David R. Evans , Sheng Teng Hsu
IPC分类号： H01G9/00 , H01L21/8242
CPC分类号： H01G9/07 , Y10S977/762 , Y10T29/417
摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.
摘要翻译：提供了形成纳米电化学（NEC）电池的方法。该方法提供了具有顶部表面的底部电极。形成纳米线贝壳。每个纳米线壳具有纳米线和套管，纳米线连接到底部电极顶表面。顶部电极形成在纳米线壳上。在顶部电极和底部电极之间形成主要腔室，部分地被第一多个纳米线壳体置换。通过蚀刻第一牺牲层，在套筒和纳米线之间形成电解质空腔。在一个方面，在底部电极顶表面和连接套筒底部开口的外壳涂层之间形成电解质腔。然后，主要和电解质空腔填充有液相或气相电解质。在不同的方面，第一牺牲层是不被蚀刻掉的固相电解质。

5. 发明授权

US07029924B2 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US07029924B2
公开(公告)日：2006-04-18
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

6. 发明授权

US06774054B1 High temperature annealing of spin coated Pr1-xCaxMnO3 thim film for RRAM application 失效
标题翻译：用于RRAM应用的旋涂Pr1-xCaxMnO3薄膜的高温退火
公开(公告)号：US06774054B1
公开(公告)日：2004-08-10
申请号：US10640728
申请日：2003-08-13
申请人： Fengyan Zhang , Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L2131
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of forming a PCMO thin film in a RRAM device includes preparing a substrate; depositing a metal barrier layer on the substrate; forming a bottom electrode on the barrier layer; spin-coating a layer of Pr1−xCaxMnO3 (PCMO) on the bottom electrode using a PCMO precursor; baking the PCMO thin film in one or more baking steps; annealing the PCMO thin film in a first annealing step after each spin-coating step; repeating the spin-coating step, the baking step and the first annealing step until the PCMO thin film has a desired thickness; annealing the PCMO thin film in a second annealing step, thereby producing a PCMO thin film having a crystalline structure of Pr1−xCaxMnO3, where 0.2
摘要翻译：在RRAM器件中形成PCMO薄膜的方法包括：制备衬底; 在衬底上沉积金属阻挡层; 在阻挡层上形成底部电极; 使用PCMO前体在底部电极上旋涂一层Pr1-xCaxMnO3（PCMO）; 在一个或多个烘烤步骤中烘烤PCMO薄膜; 在每个旋涂步骤之后的第一退火步骤中对PCMO薄膜进行退火; 重复旋涂步骤，烘烤步骤和第一退火步骤直到PCMO薄膜具有所需厚度; 在第二退火步骤中退火PCMO薄膜，从而制备具有Pr1-xCaxMnO3晶体结构的PCMO薄膜，其中0.2 <= X <= 0.5; 沉积顶部电极; 图案化顶部电极; 并完成RRAM设备。

7. 发明授权

US07645669B2 Nanotip capacitor 失效
标题翻译：纳米电容器
公开(公告)号：US07645669B2
公开(公告)日：2010-01-12
申请号：US11707712
申请日：2007-02-16
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/94 , B82Y10/00 , H01L28/91 , H01L29/66083
摘要： A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.
摘要翻译：提供了一种纳米尖端电容器和相关联的制造方法。该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

8. 发明申请

US20080191636A1 Nanotip Electrode Electroluminescence Device 有权
标题翻译：纳米线电极电致发光器件
公开(公告)号：US20080191636A1
公开(公告)日：2008-08-14
申请号：US12042983
申请日：2008-03-05
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H05B41/16 , H01J1/62
CPC分类号： H05B33/145
摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
摘要翻译：提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。在一个方面，Si磷光体层是SRSO层。响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

9. 发明授权

US07402456B2 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US07402456B2
公开(公告)日：2008-07-22
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

10. 发明授权

US07148533B2 Memory resistance film with controlled oxygen content 有权
公开(公告)号：US07148533B2
公开(公告)日：2006-12-12
申请号：US11226998
申请日：2005-09-14
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L27/96
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/016 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

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