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1. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

2. 发明授权

US07402456B2 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US07402456B2
公开(公告)日：2008-07-22
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

3. 发明授权

US07029924B2 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US07029924B2
公开(公告)日：2006-04-18
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

4. 发明授权

US06649957B2 Thin film polycrystalline memory structure 失效
标题翻译：薄膜多晶记忆结构
公开(公告)号：US06649957B2
公开(公告)日：2003-11-18
申请号：US10345725
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
IPC分类号： H01L2976
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
摘要翻译：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了形成多晶存储器结构的方法。沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

5. 发明授权

US06534326B1 Method of minimizing leakage current and improving breakdown voltage of polycrystalline memory thin films 失效
标题翻译：最小化漏电流并提高多晶记忆薄膜的击穿电压的方法
公开(公告)号：US06534326B1
公开(公告)日：2003-03-18
申请号：US10099186
申请日：2002-03-13
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
IPC分类号： H01L2100
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
摘要翻译：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了形成多晶存储器结构的方法。沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

6. 发明授权

US06849891B1 RRAM memory cell electrodes 有权
标题翻译： RRAM存储单元电极
公开(公告)号：US06849891B1
公开(公告)日：2005-02-01
申请号：US10730584
申请日：2003-12-08
申请人： Sheng Teng Hsu , Wei Pan , Fengyan Zhang , Wei-Wei Zhuang , Tingkai Li
发明人： Sheng Teng Hsu , Wei Pan , Fengyan Zhang , Wei-Wei Zhuang , Tingkai Li
IPC分类号： H01L21/28 , G11C13/00 , G11C16/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/22 , H01L29/68 , H01L39/00 , H01L43/08 , H01L45/00 , H01L29/94
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675
摘要： A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.
摘要翻译：在其上具有工作结的硅衬底上形成有一个RRAM存储单元和形成在其上的金属插塞，包括第一氧化电阻层; 第一难熔金属层; 一个CMR层; 第二难熔金属层; 和第二氧化电阻层。制造多层电极RRAM存储单元的方法包括制备硅衬底; 从由N +结和P +结组成的接头组中形成在衬底中的结; 在接头上沉积金属塞; 在金属插塞上沉积第一抗氧化层; 在第一耐氧化层上沉积第一难熔金属层; 在第一难熔金属层上沉积CMR层; 在CMR层上沉积第二难熔金属层; 在所述第二难熔金属层上沉积第二抗氧化层; 并完成RRAM存储单元。

7. 发明授权

US06457479B1 Method of metal oxide thin film cleaning 失效
标题翻译：金属氧化物薄膜清洗方法
公开(公告)号：US06457479B1
公开(公告)日：2002-10-01
申请号：US09965581
申请日：2001-09-26
申请人： Wei-Wei Zhuang , Fengyan Zhang , Sheng Teng Hsu , Tingkai Li
发明人： Wei-Wei Zhuang , Fengyan Zhang , Sheng Teng Hsu , Tingkai Li
IPC分类号： B08B600
CPC分类号： H01L21/02071 , B08B3/12 , Y10S134/902
摘要： A method of cleaning a metal oxide thin film on a silicon wafer, includes dipping the wafer in an organic solvent; drying the wafer in a nitrogen atmosphere; and stripping any photoresist from the wafer in an oxygen atmosphere under partial vacuum at a temperature of about 200° C. The wafer may also be cleaned by dipping in a polar organic solvent and subjecting the wafer to ultrasound while immersed in the solvent.
摘要翻译：一种在硅晶片上清洗金属氧化物薄膜的方法，包括将晶片浸入有机溶剂中; 在氮气气氛中干燥晶片; 并且在约200℃的温度下，在部分真空下，在氧气氛中从晶片上剥离任何光致抗蚀剂。也可以通过浸渍在极性有机溶剂中并将晶片浸入溶剂中使其超声波清洗晶片。

8. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

9. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

10. 发明授权

US06190963B1 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same 有权
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same$
标题翻译：复合铱金属 - 氧阻隔结构与难熔金属伴侣屏障及其方法相同
公开(公告)号：US06190963B1
公开(公告)日：2001-02-20
申请号：US09316661
申请日：1999-05-21
申请人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
发明人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.
摘要翻译：已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。结果，不形成铱硅化物产物，这降低了电极界面的特性。也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

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