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1. 发明申请

WO2006037056A3 STACKED DIE MODULE 审中-公开
标题翻译：堆叠模块
公开(公告)号：WO2006037056A3
公开(公告)日：2006-12-21
申请号：PCT/US2005034861
申请日：2005-09-26
申请人： FORMFACTOR INC , KHANDROS IGOR Y , MILLER CHARLES A , BARBARA BRUCE J , VASQUEZ BARBARA
发明人： KHANDROS IGOR Y , MILLER CHARLES A , BARBARA BRUCE J , VASQUEZ BARBARA
IPC分类号： H01L23/02 , H01L21/44 , H01L23/34 , H01L23/52
CPC分类号： H01L24/48 , H01L23/13 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48465 , H01L2224/4911 , H01L2224/73215 , H01L2224/73265 , H01L2224/85186 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01031 , H01L2924/01033 , H01L2924/01082 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要： Semiconductor dies (101/104/106) are stacked offset from one another so that terminals (122/124/126) located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections (130/132/134) may connect terminals on one die with terminals on another die and the stack may be disposed on a wiring substrate (112) to which the terminals of the dies may be electrically connected.
摘要翻译：半导体管芯（101/104/106）彼此堆叠地偏置，使得沿着每个管芯的两个边缘定位的端子（122/124/126）被暴露。具有端子的模具的两个边缘可以沿相同的方向定向。电连接（130/132/134）可以将一个管芯上的端子与另一个管芯上的端子连接，并且堆叠可以布置在可以电连接管芯的端子的布线基板（112）上。

2. 发明申请

WO2006102006A3 VOLTAGE FAULT DETECTION AND PROTECTION 审中-公开
标题翻译：电压故障检测和保护
公开(公告)号：WO2006102006A3
公开(公告)日：2009-04-09
申请号：PCT/US2006009575
申请日：2006-03-16
申请人： FORMFACTOR INC , MILLER CHARLES A , BARBARA BRUCE J
发明人： MILLER CHARLES A , BARBARA BRUCE J
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R1/36 , G01R31/2889
摘要： A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.
摘要翻译：故障检测和保护电路可以包括比较电路（例如，比较器或检测器），其可以连接到向所测试的电子设备供电的电力线。比较电路可以被配置为检测电力线短路到地的故障。例如，被测试的电子设备可能具有其电源端子短路到地的故障。在检测到这种故障时，比较电路激活将电力线上的电容器或其他能量存储装置分流到地的一个或多个开关。比较电路可以替代地或者另外激活一个或多个开关，该开关断开供给被测试的电子设备的电源与接触电子设备的探针的电源。

3. 发明申请

WO2007035664A3 APPARATUS AND METHOD OF TESTING SINGULATED DIES 审中-公开
标题翻译：装置和测试方法
公开(公告)号：WO2007035664A3
公开(公告)日：2009-04-30
申请号：PCT/US2006036336
申请日：2006-09-18
申请人： FORMFACTOR INC , DOZIER II THOMAS H , ELDRIDGE BENJAMIN N , HSU DAVID S , KHANDROS IGOR Y , MILLER CHARLES A
发明人： DOZIER II THOMAS H , ELDRIDGE BENJAMIN N , HSU DAVID S , KHANDROS IGOR Y , MILLER CHARLES A
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/2893 , G01R31/31905
摘要： An exemplary die carrier is disclosed. In some embodiments, the die carrier can hold a plurality of singulated dies while the dies are tested. The dies can be arranged on the carrier in a pattern that facilities testing the dies. The carrier can be configured to allow interchangeable interfaces to different testers to be attached to and detached from the carrier. The carrier can also be configured as a shipping container for the dies.
摘要翻译：公开了一种示例性的模具载体。在一些实施例中，模具载体可以在测试模具的同时保持多个单个模具。模具可以以对模具进行测试的模式布置在载体上。载体可以被配置为允许不同的测试仪的可互换的接口被附接到载体上并与载体分离。载体也可以被配置为模具的运输容器。

4. 发明申请

WO2007146581A2 METHOD OF EXPANDING TESTER DRIVE AND MEASUREMENT CAPABILITY 审中-公开
标题翻译：扩展测试仪驱动和测量能力的方法
公开(公告)号：WO2007146581A2
公开(公告)日：2007-12-21
申请号：PCT/US2007069798
申请日：2007-05-25
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07342
摘要： A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.
摘要翻译：探针卡组件可以包括接口，其可被配置为从测试仪接收用于测试电子设备的测试信号。探针卡组件还可以包括用于接触电子设备的探针和用于将测试信号驱动到探针中的探针的电子驱动器电路。

5. 发明申请

WO2005101038A3 WIRELESS TEST CASSETTE 审中-公开
标题翻译：无线测试CASSETTE
公开(公告)号：WO2005101038A3
公开(公告)日：2005-12-15
申请号：PCT/US2005011849
申请日：2005-04-08
申请人： FORMFACTOR INC , ELDRIDGE BENJAMIN N , KHANDROS IGOR Y , MILLER CHARLES A , SPORCK NICHOLAS A
发明人： ELDRIDGE BENJAMIN N , KHANDROS IGOR Y , MILLER CHARLES A , SPORCK NICHOLAS A
IPC分类号： G01R1/073 , G01R31/02 , G01R31/26
CPC分类号： G01R1/0491 , G01R1/073 , G01R31/3025
摘要： A base controller (210) disposed in a test cassette (110) receives test data for testing a plurality of electronic devices (236a,236b). The base controller wirelessly transmits the test data to a plurality of wireless test control chips (214a,214b,214c,214d,214e,214f,214g), which write the test data to each of the electronic devices. The wireless test control chips (214a,214b,214c,214d,214e,214f,214g), then read response data generated by the electronic devices (236a, 236b), and the wireless test control chips wirelessly transmit the response data to the base controller (210).
摘要翻译：设置在测试盒（110）中的基本控制器（210）接收用于测试多个电子设备（236a，236b）的测试数据。基站控制器将测试数据无线发送到多个无线测试控制芯片（214a，214b，214c，214d，214e，214f，214g），其将测试数据写入每个电子设备。无线测试控制芯片（214a，214b，214c，214d，214e，214f，214g）然后读取由电子设备（236a，236b）产生的响应数据，并且无线测试控制芯片将响应数据无线地发送到基站控制器（210）。

6. 发明申请

WO2007146583A3 METHOD OF DESIGNING AN APPLICATION SPECIFIC PROBE CARD TEST SYSTEM 审中-公开
标题翻译：设计应用特定探头卡测试系统的方法
公开(公告)号：WO2007146583A3
公开(公告)日：2009-02-26
申请号：PCT/US2007069810
申请日：2007-05-25
申请人： FORMFACTOR INC , MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
发明人： MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
IPC分类号： G01R31/02 , G01R1/073 , G01R1/36 , G01R31/28 , G01R31/319 , G01R35/00
CPC分类号： G01R31/31905 , G01R31/2889 , G01R31/31926 , G01R35/00
摘要： A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs , even during the test process (2) to generate test vector signals to provide to the ICs , and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.
摘要翻译：提供了一种用于在晶片测试系统中设计和编程具有板上可编程控制器的探针卡的方法。引入可编程控制器的考虑因素包括在CAD晶圆布局和探针卡设计过程中。 CAD设计进一步加载到可编程控制器（例如FPGA）中以对其进行编程：（1）甚至在测试过程（2）期间控制信号到特定IC的方向，以产生测试向量信号以提供给IC，和（3）从接收信号接收测试信号和处理测试结果。在一些实施例中，仅提供老化测试以限制所需的测试系统电路，使得利用探针卡上的可编程控制器，可以从常规测试设备消除或显着减少探针卡外部的文本设备。

7. 发明申请

WO2006010120A3 A METHOD AND APPARATUS FOR CALIBRATING AND/OR DESKEWING COMMUNICATIONS CHANNELS 审中-公开
标题翻译：一种用于校准和/或消除通信通道的方法和装置
公开(公告)号：WO2006010120A3
公开(公告)日：2007-03-29
申请号：PCT/US2005024532
申请日：2005-07-11
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G06K5/04 , G01R31/28
CPC分类号： G01R35/005 , G01R31/3016 , G01R31/31723 , G01R31/318511 , G01R31/3191 , G01R31/31937
摘要： A series of pulses may be driven down each drive channel ("A", and 514, 516, 518, Fig. 5), which creates a series of composite pulses at the output of the buffer (532). Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted (406) until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels (544 and 546), and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels.
摘要翻译：可以沿着每个驱动通道（图A中的“A”和“514,516,518”）驱动一系列脉冲，这在缓冲器（532）的输出处产生一系列复合脉冲。每个复合脉冲是从驱动通道驱动的各个脉冲的组合。可以调整与驱动通道相关联的定时偏移（406），直到复合脉冲的各个脉冲对准或紧密对准。这些定时偏移校准和/或校正驱动通道，补偿通过驱动通道传播延迟的差异。复合脉冲可以通过比较通道（544和546）反馈给测试仪，并且与每个比较通道的比较信号相关的偏移量可以对准复合脉冲，该复合脉冲校准和/或对比比较通道。

8. 发明申请

WO2005076885A3 CONTACTLESS INTERFACING OF TEST SIGNALS WITH A DEVICE UNDER TEST 审中-公开
标题翻译：与测试设备的测试信号的接触式接口
公开(公告)号：WO2005076885A3
公开(公告)日：2006-12-21
申请号：PCT/US2005003360
申请日：2005-02-02
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G01R31/302 , G01R1/00 , G01R1/02 , G01R31/02 , G01R31/26 , G01R31/308 , G01R31/311
CPC分类号： G01R1/0491 , G01R1/07 , G01R1/07378 , G01R31/3025
摘要： An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.
摘要翻译：接口设备从测试器接收测试数据。表示测试数据的信号通过接口设备和被测设备上的电磁耦合结构发送到被测设备。被测设备处理测试数据并产生响应数据。表示响应数据的信号通过被测设备和接口设备上的电磁耦合结构传送到接口设备。

9. 发明申请

WO2006073737A3 A METHOD AND APPARATUS FOR INCREASING THE OPERATING FREQUENCY OF A SYSTEM FOR TESTING ELECTRONIC DEVICES 审中-公开
标题翻译：一种用于增加测试电子设备的系统的操作频率的方法和装置
公开(公告)号：WO2006073737A3
公开(公告)日：2007-03-08
申请号：PCT/US2005045583
申请日：2005-12-15
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/31905
摘要： A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.
摘要翻译：测试系统包括通信信道，探测器中的终端接触要测试的电子设备的输入端。在探头和地之间的通信通道之间连接一个电阻。该电阻降低了端子的输入电阻，从而减小了输入端子的上升和下降时间。信道可以在具有多个路径的分支中终止，其中每个路径用用于接触待测试的电子设备上的终端的探针终止。隔离电阻包括在分支中，以防止一个输入端子的故障传播到其他输入端子。在每个分支中设置有分流电阻器，这降低了端子的输入电阻，从而减小了输入端子的上升和下降时间。分流电阻器的尺寸也可以减小，最小化或消除信道反射信号的反射。

10. 发明申请

WO2006068938A2 BI-DIRECTIONAL BUFFER FOR INTERFACING TEST SYSTEM CHANNEL 审中-公开
标题翻译：用于接口测试系统通道的双向缓冲器
公开(公告)号：WO2006068938A2
公开(公告)日：2006-06-29
申请号：PCT/US2005045610
申请日：2005-12-15
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/31713
摘要： An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.
摘要翻译：在DUT和测试系统控制器之间的晶片测试系统的通道中提供射极跟随器或源极跟随器晶体管，以使得低功率DUT能够驱动测试系统通道。在射极跟随器晶体管的基极和发射极之间包括一个旁路电阻，以便能够在DUT通道和测试系统控制器之间提供双向信号，以及执行参数测试。射极跟随器晶体管和旁路电阻可以在探针卡上提供，并具有包括在测试系统控制器中的下拉终端电路。测试系统控制器可以为射极跟随器晶体管的基极到发射极电压降提供补偿。

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