会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • VOLTAGE FAULT DETECTION AND PROTECTION
    • 电压故障检测和保护
    • WO2006102006A3
    • 2009-04-09
    • PCT/US2006009575
    • 2006-03-16
    • FORMFACTOR INCMILLER CHARLES ABARBARA BRUCE J
    • MILLER CHARLES ABARBARA BRUCE J
    • G01R31/02G01R31/26
    • G01R1/36G01R31/2889
    • A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.
    • 故障检测和保护电路可以包括比较电路(例如,比较器或检测器),其可以连接到向所测试的电子设备供电的电力线。 比较电路可以被配置为检测电力线短路到地的故障。 例如,被测试的电子设备可能具有其电源端子短路到地的故障。 在检测到这种故障时,比较电路激活将电力线上的电容器或其他能量存储装置分流到地的一个或多个开关。 比较电路可以替代地或者另外激活一个或多个开关,该开关断开供给被测试的电子设备的电源与接触电子设备的探针的电源。
    • 7. 发明申请
    • A METHOD AND APPARATUS FOR CALIBRATING AND/OR DESKEWING COMMUNICATIONS CHANNELS
    • 一种用于校准和/或消除通信通道的方法和装置
    • WO2006010120A3
    • 2007-03-29
    • PCT/US2005024532
    • 2005-07-11
    • FORMFACTOR INCMILLER CHARLES A
    • MILLER CHARLES A
    • G06K5/04G01R31/28
    • G01R35/005G01R31/3016G01R31/31723G01R31/318511G01R31/3191G01R31/31937
    • A series of pulses may be driven down each drive channel ("A", and 514, 516, 518, Fig. 5), which creates a series of composite pulses at the output of the buffer (532). Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted (406) until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels (544 and 546), and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels.
    • 可以沿着每个驱动通道(图A中的“A”和“514,516,518”)驱动一系列脉冲,这在缓冲器(532)的输出处产生一系列复合脉冲。 每个复合脉冲是从驱动通道驱动的各个脉冲的组合。 可以调整与驱动通道相关联的定时偏移(406),直到复合脉冲的各个脉冲对准或紧密对准。 这些定时偏移校准和/或校正驱动通道,补偿通过驱动通道传播延迟的差异。 复合脉冲可以通过比较通道(544和546)反馈给测试仪,并且与每个比较通道的比较信号相关的偏移量可以对准复合脉冲,该复合脉冲校准和/或对比比较通道。
    • 9. 发明申请
    • A METHOD AND APPARATUS FOR INCREASING THE OPERATING FREQUENCY OF A SYSTEM FOR TESTING ELECTRONIC DEVICES
    • 一种用于增加测试电子设备的系统的操作频率的方法和装置
    • WO2006073737A3
    • 2007-03-08
    • PCT/US2005045583
    • 2005-12-15
    • FORMFACTOR INCMILLER CHARLES A
    • MILLER CHARLES A
    • G01R31/02
    • G01R31/2889G01R31/31905
    • A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.
    • 测试系统包括通信信道,探测器中的终端接触要测试的电子设备的输入端。 在探头和地之间的通信通道之间连接一个电阻。 该电阻降低了端子的输入电阻,从而减小了输入端子的上升和下降时间。 信道可以在具有多个路径的分支中终止,其中每个路径用用于接触待测试的电子设备上的终端的探针终止。 隔离电阻包括在分支中,以防止一个输入端子的故障传播到其他输入端子。 在每个分支中设置有分流电阻器,这降低了端子的输入电阻,从而减小了输入端子的上升和下降时间。 分流电阻器的尺寸也可以减小,最小化或消除信道反射信号的反射。
    • 10. 发明申请
    • BI-DIRECTIONAL BUFFER FOR INTERFACING TEST SYSTEM CHANNEL
    • 用于接口测试系统通道的双向缓冲器
    • WO2006068938A2
    • 2006-06-29
    • PCT/US2005045610
    • 2005-12-15
    • FORMFACTOR INCMILLER CHARLES A
    • MILLER CHARLES A
    • G01R31/02
    • G01R31/2889G01R31/31713
    • An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.
    • 在DUT和测试系统控制器之间的晶片测试系统的通道中提供射极跟随器或源极跟随器晶体管,以使得低功率DUT能够驱动测试系统通道。 在射极跟随器晶体管的基极和发射极之间包括一个旁路电阻,以便能够在DUT通道和测试系统控制器之间提供双向信号,以及执行参数测试。 射极跟随器晶体管和旁路电阻可以在探针卡上提供,并具有包括在测试系统控制器中的下拉终端电路。 测试系统控制器可以为射极跟随器晶体管的基极到发射极电压降提供补偿。