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1. 发明申请

US20050147751A1 Deposition methods 失效
公开(公告)号：US20050147751A1
公开(公告)日：2005-07-07
申请号：US11075017
申请日：2005-03-08
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： C23C16/44 , C23C16/455 , C23C14/00 , C23C16/00
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/455
摘要： A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.

2. 发明申请

US20060205228A1 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US20060205228A1
公开(公告)日：2006-09-14
申请号：US11414407
申请日：2006-04-28
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间组合物单层，随后是与中间体组合物反应所需的沉积组合物，统称为将多种不同的组合物沉积前体流到沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

3. 发明申请

US20060205227A1 Atomic layer deposition methods 有权
公开(公告)号：US20060205227A1
公开(公告)日：2006-09-14
申请号：US11413438
申请日：2006-04-28
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri , Gurtej Sandhu , F. Gealy , Chris Carlson
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

4. 发明申请

US20050145918A1 Methods of forming capacitors and electronic devices 有权
标题翻译：形成电容器和电子设备的方法
公开(公告)号：US20050145918A1
公开(公告)日：2005-07-07
申请号：US11050088
申请日：2005-02-03
申请人： F. Gealy , Garo Derderian , Chris Carlson
发明人： F. Gealy , Garo Derderian , Chris Carlson
IPC分类号： H01L21/02 , H01L27/108
CPC分类号： H01L28/65 , H01L28/75 , H01L28/91
摘要： A method of forming a capacitor includes forming a first conductive capacitor electrode layer over a substrate. The first electrode layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a capacitor dielectric layer onto the outer surface. A conductive capacitor electrode layer is formed over the capacitor dielectric layer. A method of forming an electronic device includes forming a conductive layer over a substrate. The conductive layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a dielectric layer onto the outer surface.
摘要翻译：形成电容器的方法包括在衬底上形成第一导电电容器电极层。第一电极层具有包含元素和合金形式中的至少一种的贵金属的外表面。包含金属有机物沉积前体和有机溶剂的气体混合物在有效地将电容器介电层沉积到外表面上的条件下进料至外表面。在电容器电介质层上形成导电电容电极层。形成电子器件的方法包括在衬底上形成导电层。导电层具有包含元素和合金形式中的至少一种的贵金属的外表面。将包含金属有机物沉积前体和有机溶剂的气态混合物在有效沉积介电层到外表面上的条件下进料至外表面。

5. 发明授权

US07390710B2 Protection of tunnel dielectric using epitaxial silicon 有权
标题翻译：使用外延硅保护隧道电介质
公开(公告)号：US07390710B2
公开(公告)日：2008-06-24
申请号：US10932795
申请日：2004-09-02
申请人： Garo Derderian , Nirmal Ramaswamy
发明人： Garo Derderian , Nirmal Ramaswamy
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336
摘要： Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.
摘要翻译：使用外延硅层来保护浮栅存储器单元的隧道介电层免于在形成浅沟槽隔离（STI）区域期间的过度氧化或去除。在沟槽形成之后，外延硅层从隧道介电层的相对侧上的含硅层生长，从而允许其厚度被限制为隧道介电层的厚度的大约二分之一。外延硅可以在用电介质材料填充沟槽之前被氧化，或者在氧化至少覆盖隧道介电层的端部的外延硅之前可能发生电介质填充。

6. 发明申请

US20070148932A9 Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition 失效
标题翻译：使用原子层沉积形成铌和/或含钒层的系统和方法
公开(公告)号：US20070148932A9
公开(公告)日：2007-06-28
申请号：US10923315
申请日：2004-08-20
申请人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
发明人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
IPC分类号： H01L21/20
CPC分类号： H01L21/02205 , C23C16/405 , C23C16/45553 , H01L21/02175 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31604 , H01L28/90
摘要： A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
摘要翻译：使用一种或多种包括铌和/或钒的前体化合物在基板上，特别是用于制造半导体或存储器件结构的半导体衬底或衬底组件中形成（以及用于形成）含金属层的方法以及使用包括多个沉积循环的原子层沉积工艺。

7. 发明申请

US20070141835A1 Methods of fabricating interconnects for semiconductor components 有权
标题翻译：制造半导体元件互连的方法
公开(公告)号：US20070141835A1
公开(公告)日：2007-06-21
申请号：US11705897
申请日：2007-02-13
申请人： Kyle Kirby , Shuang Meng , Garo Derderian
发明人： Kyle Kirby , Shuang Meng , Garo Derderian
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： C23C16/34 , C23C16/45525 , C23C18/1608 , C23C18/1879 , C23C18/36 , H01L21/28562 , H01L21/288 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
摘要翻译：一方面，本发明包括制造用于半导体部件的互连的方法。提供半导体衬底，并且形成完全贯穿衬底的开口。第一种材料在小于或等于约200℃的温度下沿着开口的侧壁沉积。沉积可以包括原子层沉积和化学气相沉积中的一个或两个，并且第一材料可以包括金属氮化物。在第一材料的表面上形成焊料润湿材料。焊料润湿材料可以包括例如镍。随后，在开口内和焊料润湿材料之上提供焊料。

8. 发明申请

US20070138529A1 MIS capacitor and method of formation 有权
标题翻译： MIS电容器和形成方法
公开(公告)号：US20070138529A1
公开(公告)日：2007-06-21
申请号：US11545481
申请日：2006-10-11
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L27/10852 , H01L28/55 , H01L28/84 , H01L28/91 , H01L29/94
摘要： An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
摘要翻译：公开了具有低泄漏和高电容的MIS电容器。形成半球状晶粒多晶硅层（HSG）作为下电极。在电介质形成之前，半球状晶粒多晶硅层可以任选地进行氮化或退火工艺。在半球形颗粒上制造氧化铝（Al 2 O 3 3）的介电层或氧化铝和其它金属氧化物电介质材料的交错层的复合叠层多晶硅层和可选的氮化或退火工艺后。氧化铝（Al 2 O 3 3）的电介质层或氧化铝复合叠层可以任选地进行后沉积处理以进一步增加电容并减小漏电流。通过沉积技术或通过原子层沉积在电介质层或复合叠层上形成金属氮化物上电极。

9. 发明申请

US20070063262A1 NAND memory arrays 审中-公开
标题翻译： NAND存储器阵列
公开(公告)号：US20070063262A1
公开(公告)日：2007-03-22
申请号：US11601095
申请日：2006-11-17
申请人： Michael Violette , Garo Derderian , Todd Abbott
发明人： Michael Violette , Garo Derderian , Todd Abbott
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.
摘要翻译： NAND存储器阵列具有多行存储器单元和多列存储器单元的NAND串。每个NAND串通过相应列的漏极选择栅选择性地连接到位线。每个漏极选择栅极具有形成在存储器阵列的半导体衬底上的第一电介质层和形成在第一介电层上的控制栅极。每个NAND串的每个存储单元具有形成在与第一介电层相邻的基板上的第二介质层，形成在第二介电层上的浮动栅极，形成在浮置栅极上的第三介电层，以及控制栅极形成在第三电介质层上。第一电介质层比第二电介质层厚。

10. 发明申请

US20060257584A1 Atomic layer deposition method of depositing an oxide on a substrate 有权
标题翻译：在衬底上沉积氧化物的原子层沉积方法
公开(公告)号：US20060257584A1
公开(公告)日：2006-11-16
申请号：US11491383
申请日：2006-07-20
申请人： Garo Derderian , Shuang Meng , Danny Dynka
发明人： Garo Derderian , Shuang Meng , Danny Dynka
IPC分类号： H05H1/24 , C23C16/00
CPC分类号： C23C16/45542 , C23C16/402 , C23C16/403 , C23C16/407 , C23C16/45531
摘要： The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed onto the substrate to form a first species monolayer within the deposition chamber from a gaseous precursor. The chemisorbed first species is contacted with remote plasma oxygen derived at least in part from at least one of O2 and O3 and with remote plasma nitrogen effective to react with the first species to form a monolayer comprising an oxide of a component of the first species monolayer. The chemisorbing and the contacting with remote plasma oxygen and with remote plasma nitrogen are successively repeated effective to form porous oxide on the substrate. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在衬底上沉积氧化物的原子层沉积方法。在一个实施方式中，衬底位于沉积室内。第一种物质被化学吸附到基底上以在气相前体的沉积室内形成第一物质单层。化学吸附的第一物质与至少部分从O 2和O 3 3中的至少一个导出的远程等离子体氧接触，并且与远程等离子体氮有效地与第一物质反应物质形成包含第一物质单层的组分的氧化物的单层。连续重复化学吸附和与远程等离子体氧和远程等离子体氮的接触，以在衬底上形成多孔氧化物。考虑了其他方面和实现。

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