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1. 发明申请

US20070138529A1 MIS capacitor and method of formation 有权
标题翻译： MIS电容器和形成方法
公开(公告)号：US20070138529A1
公开(公告)日：2007-06-21
申请号：US11545481
申请日：2006-10-11
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L27/10852 , H01L28/55 , H01L28/84 , H01L28/91 , H01L29/94
摘要： An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
摘要翻译：公开了具有低泄漏和高电容的MIS电容器。形成半球状晶粒多晶硅层（HSG）作为下电极。在电介质形成之前，半球状晶粒多晶硅层可以任选地进行氮化或退火工艺。在半球形颗粒上制造氧化铝（Al 2 O 3 3）的介电层或氧化铝和其它金属氧化物电介质材料的交错层的复合叠层多晶硅层和可选的氮化或退火工艺后。氧化铝（Al 2 O 3 3）的电介质层或氧化铝复合叠层可以任选地进行后沉积处理以进一步增加电容并减小漏电流。通过沉积技术或通过原子层沉积在电介质层或复合叠层上形成金属氮化物上电极。

2. 发明申请

US20050042374A1 Methods of depositing materials over substrates, and methods of forming layers over substrates 失效
标题翻译：在衬底上沉积材料的方法，以及在衬底上形成层的方法
公开(公告)号：US20050042374A1
公开(公告)日：2005-02-24
申请号：US10652224
申请日：2003-08-22
申请人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri
发明人： Demetrius Sarigiannis , Garo Derderian , Cem Basceri
IPC分类号： C23C16/40 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/06
CPC分类号： C23C16/45525 , C23C16/40 , C23C16/448 , Y10S427/101
摘要： The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is utilized to introduce multiple precursors into the reaction chamber during ALD. The invention can be utilized to form any of various materials, including metal-containing materials, such as, for example, metal oxides, metal nitrides, and materials consisting of metal. Metal oxides can be formed by utilizing a supercritical fluid can be utilized to introduce a metal-containing precursor into reaction chamber, with the precursor then forming a metal-containing layer over a surface of a substrate. Subsequently, the metal-containing layer can be reacted with oxygen to convert at least some of the metal within the layer to metal oxide.
摘要翻译：本发明包括利用超临界流体将前体引入反应室的方法。在一些方面，使用超临界流体在ALD期间将至少一种前体引入室中，并且在特定方面，超临界流体用于在ALD期间将多种前体引入反应室。本发明可用于形成任何各种材料，包括含金属的材料，例如金属氧化物，金属氮化物和由金属组成的材料。可以通过利用超临界流体来形成金属氧化物，以将含金属的前体引入反应室，然后前体在基材的表面上形成含金属的层。随后，含金属层可以与氧反应以将该层内的至少一些金属转化为金属氧化物。

3. 发明授权

US06596583B2 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
公开(公告)号：US06596583B2
公开(公告)日：2003-07-22
申请号：US10002906
申请日：2001-10-29
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

4. 发明申请

US20060076597A1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 审中-公开
公开(公告)号：US20060076597A1
公开(公告)日：2006-04-13
申请号：US11235866
申请日：2005-09-26
申请人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L29/94
CPC分类号： H01L28/84 , H01L21/02183 , H01L21/02197 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

5. 发明申请

US20050126585A1 Method of removing residual contaminants from an environment 有权
标题翻译：从环境中清除残留污染物的方法
公开(公告)号：US20050126585A1
公开(公告)日：2005-06-16
申请号：US10734525
申请日：2003-12-11
申请人： Demetrius Sarigiannis , Cem Basceri , Christopher Hill , Garo Derderian
发明人： Demetrius Sarigiannis , Cem Basceri , Christopher Hill , Garo Derderian
IPC分类号： B08B9/00 , C23C14/56 , C23C16/44
CPC分类号： C23C16/4401 , C23C14/564
摘要： A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.
摘要翻译：一种在含卤素环境中减少卤化物质的量的方法。该方法包括将铝化合物引入含卤素的环境中，使铝化合物与卤化物反应形成气态反应产物，并从气氛中除去气态反应产物。铝化合物可以是三烷基铝化合物，烷烃，烷基铝氢化物，烷基铝卤化物，烷基铝倍半卤化物或倍半卤化铝。铝化合物可替代地形成固体铝产物，其沉积在与含卤素环境相关的表面上或其上设置的半导体上。将卤化物掺入固体铝产品中，形成惰性膜，卤化物质被捕获在该惰性膜中。

6. 发明申请

US20050048792A1 Atomic layer deposition apparatus 审中-公开
标题翻译：原子层沉积装置
公开(公告)号：US20050048792A1
公开(公告)日：2005-03-03
申请号：US10954845
申请日：2004-09-29
申请人： Garo Derderian , Cem Basceri , Gurtej Sandhu , Demetrius Sarigiannis
发明人： Garo Derderian , Cem Basceri , Gurtej Sandhu , Demetrius Sarigiannis
IPC分类号： C30B25/00 , C30B35/00 , H01L21/31
CPC分类号： C30B35/00 , C30B25/00 , C30B29/68
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A fixed volume first precursor gas charge is provided within a gas flow path to the deposition chamber. A fixed volume purge gas charge is provided within the gas flow path serially upstream of the first precursor gas charge. The first precursor gas charge and the purge gas charge are serially flowed along the gas flow path to the substrate within the deposition chamber effective to form a monolayer on the substrate and purge at least some of the first precursor gas from the substrate. Apparatus are also disclosed.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。在到达沉积室的气体流动路径内提供固定体积的第一前体气体进料。在第一前体气体装料的串联的气体流动路径内提供固定体积的吹扫气体装料。第一前体气体装料和吹扫气体装料沿着气体流动路径顺序地流动到沉积室内的基板，有效地在基板上形成单层，并且从基板清除至少一些第一前体气体。还公开了装置。

7. 发明申请

US20050039674A1 Atomic layer deposition method 失效
标题翻译：原子层沉积法
公开(公告)号：US20050039674A1
公开(公告)日：2005-02-24
申请号：US10956925
申请日：2004-09-30
申请人： Paul Castovillo , Cem Basceri , Garo Derderian , Gurtej Sandhu
发明人： Paul Castovillo , Cem Basceri , Garo Derderian , Gurtej Sandhu
IPC分类号： C23C16/34 , C23C14/06 , C23C14/08 , C23C16/40 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/285 , H01L21/316 , H01L21/768 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/8238
CPC分类号： C30B25/14 , C23C14/0641 , C23C14/081 , C23C16/34 , C23C16/403 , C23C16/45527 , C23C16/45531
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。在形成第一单层之后，反应性中间气体流到沉积室内的衬底。反应性中间体气体能够与在反应性中间体气体流动的条件下流动的第一前体的中间反应副产物反应。在流动反应性中间气体之后，第二前体气体流到沉积室内的衬底，有效地在第一单层上形成第二单层。考虑了其他方面和实现。

8. 发明申请

US20050020026A1 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and semiconductor constructions 失效
标题翻译：电容器结构，半导体结构以及形成电触点和半导体结构的方法
公开(公告)号：US20050020026A1
公开(公告)日：2005-01-27
申请号：US10917894
申请日：2004-08-13
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/00 , H01L21/20
CPC分类号： H01L21/7687 , H01L21/76877 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , Y10S438/964
摘要： The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.
摘要翻译：本发明包括形成半导体结构的方法。提供半导体衬底，并且形成由半导体衬底支撑的导电节点。第一导电材料形成在导电节点上并成形为容器。容器具有在其中延伸的开口和靠近开口的上表面。容器开口至少部分地填充有绝缘材料。第二导电材料形成在至少部分填充的容器开口上并且物理地抵靠容器的上表面。本发明还包括半导体结构。

9. 发明申请

US20050017359A1 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and semiconductor constructions 有权
公开(公告)号：US20050017359A1
公开(公告)日：2005-01-27
申请号：US10917705
申请日：2004-08-13
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L21/7687 , H01L21/76877 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , Y10S438/964
摘要： The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

10. 发明授权

US07253076B1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
标题翻译：含有钌和钨的层的形成方法和集成电路结构
公开(公告)号：US07253076B1
公开(公告)日：2007-08-07
申请号：US09590795
申请日：2000-06-08
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
摘要翻译：具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的，产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。该层可以形成在下面的导电层上。处理可以在惰性环境或还原环境中进行。可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。氧化环境中的处理也可以进行以钝化粗糙层。可以使用粗糙化的钌层来形成增强表面积的导电层。所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。在另一种方法中，提供氮化钨层作为这种电容器的第一电极。电容器或至少氮化钨层被退火以增加电容器的电容。

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