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1. 发明申请

US20060258093A1 NAND memory arrays 审中-公开
标题翻译： NAND存储器阵列
公开(公告)号：US20060258093A1
公开(公告)日：2006-11-16
申请号：US11486596
申请日：2006-07-14
申请人： Michael Violette , Garo Derderian , Todd Abbott
发明人： Michael Violette , Garo Derderian , Todd Abbott
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： A NAND memory array has a first dielectric layer formed on a first portion of a semiconductor substrate and a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer. The first dielectric layer is thicker than the second dielectric layer. A first gate stack is formed on the first dielectric layer to form a drain select gate. A string of second gate stacks is formed on the second dielectric layer to form a NAND string of floating-gate memory cells. A first end of the NAND string is coupled in series with the drain select gate. A third gate stack is formed on the second dielectric layer to form a source select gate. A second end of the NAND string is coupled in series with the source select gate.
摘要翻译： NAND存储器阵列具有形成在半导体衬底的第一部分上的第一电介质层和形成在半导体衬底的第二部分上且与第一电介质层相邻的第二电介质层。第一电介质层比第二电介质层厚。在第一电介质层上形成第一栅极叠层以形成漏极选择栅极。在第二电介质层上形成一串第二栅极叠层，以形成浮栅存储器单元的NAND串。 NAND串的第一端与漏极选择栅极串联耦合。在第二电介质层上形成第三栅极叠层以形成源选择栅极。 NAND串的第二端与源极选择栅极串联耦合。

2. 发明申请

US20060040447A1 NAND memory arrays and methods 有权
标题翻译： NAND存储器阵列和方法
公开(公告)号：US20060040447A1
公开(公告)日：2006-02-23
申请号：US10920561
申请日：2004-08-18
申请人： Michael Violette , Garo Derderian , Todd Abbott
发明人： Michael Violette , Garo Derderian , Todd Abbott
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.
摘要翻译：提供NAND存储器阵列和方法。在形成在NAND存储器阵列的衬底上的第一电介质层上形成多个第一栅极叠层。形成在其上的第一介电层和多个第一栅极堆叠形成存储器阵列的存储器单元的NAND串。在与第一介电层相邻的基板上形成的第二电介质层上形成第二栅极叠层。其上形成有第二栅极堆叠的第二介电层形成与NAND串的端部相邻的漏极选择栅极。第二电介质层比第一电介质层厚。

3. 发明申请

US20070063262A1 NAND memory arrays 审中-公开
标题翻译： NAND存储器阵列
公开(公告)号：US20070063262A1
公开(公告)日：2007-03-22
申请号：US11601095
申请日：2006-11-17
申请人： Michael Violette , Garo Derderian , Todd Abbott
发明人： Michael Violette , Garo Derderian , Todd Abbott
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.
摘要翻译： NAND存储器阵列具有多行存储器单元和多列存储器单元的NAND串。每个NAND串通过相应列的漏极选择栅选择性地连接到位线。每个漏极选择栅极具有形成在存储器阵列的半导体衬底上的第一电介质层和形成在第一介电层上的控制栅极。每个NAND串的每个存储单元具有形成在与第一介电层相邻的基板上的第二介质层，形成在第二介电层上的浮动栅极，形成在浮置栅极上的第三介电层，以及控制栅极形成在第三电介质层上。第一电介质层比第二电介质层厚。

4. 发明授权

US07276414B2 NAND memory arrays and methods 有权
标题翻译： NAND存储器阵列和方法
公开(公告)号：US07276414B2
公开(公告)日：2007-10-02
申请号：US10920561
申请日：2004-08-18
申请人： Michael Violette , Garo Derderian , Todd R. Abbott
发明人： Michael Violette , Garo Derderian , Todd R. Abbott
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.
摘要翻译：提供NAND存储器阵列和方法。在形成在NAND存储器阵列的衬底上的第一电介质层上形成多个第一栅极叠层。形成在其上的第一介电层和多个第一栅极堆叠形成存储器阵列的存储器单元的NAND串。在与第一介电层相邻的基板上形成的第二电介质层上形成第二栅极叠层。其上形成有第二栅极堆叠的第二介电层形成与NAND串的端部相邻的漏极选择栅极。第二电介质层比第一电介质层厚。

5. 发明申请

US20060006456A1 Memory cells and select gates of NAND memory arrays 有权
标题翻译： NAND存储器阵列的存储单元和选择门
公开(公告)号：US20060006456A1
公开(公告)日：2006-01-12
申请号：US11215902
申请日：2005-08-31
申请人： Todd Abbott , Michael Violette
发明人： Todd Abbott , Michael Violette
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are formed on sidewalls of the first conductive layer and are located between an upper surface of the first conductive layer and the first dielectric layer. A second dielectric layer overlies the first conductive layer and the conductive spacers. A second conductive layer is formed on the second dielectric layer. A third conducive layer is formed on the second conductive layer, passes though a portion of the second conductive layer and the second dielectric layer, and contacts the first conductive layer. The third conductive layer electrically connects the first and second conductive layers.
摘要翻译： NAND存储器阵列的选择栅极具有形成在半导体衬底上的第一电介质层。在第一电介质层上形成第一导电层。导电间隔物形成在第一导电层的侧壁上，并且位于第一导电层的上表面和第一介电层之间。第二电介质层覆盖在第一导电层和导电间隔物之间。在第二电介质层上形成第二导电层。第三导电层形成在第二导电层上，穿过第二导电层和第二介电层的一部分，并与第一导电层接触。第三导电层电连接第一和第二导电层。

6. 发明申请

US20050285178A1 Formation of memory cells and select gates of NAND memory arrays 有权
标题翻译：存储单元的形成和NAND存储器阵列的选择门
公开(公告)号：US20050285178A1
公开(公告)日：2005-12-29
申请号：US10878799
申请日：2004-06-28
申请人： Todd Abbott , Michael Violette
发明人： Todd Abbott , Michael Violette
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the second conductive layer self align with and are disposed on sidewalls of the first conductive layer. The first conductive layer is disposed on a first dielectric layer that is disposed on a substrate. A second dielectric layer is formed overlying the first conductive layer and the remaining portions of the second conductive layer. A third conductive layer is formed on the second dielectric layer. A fourth conductive layer is formed on the third conductive layer. For the select gate, the fourth conductive layer also passes through the third conductive layer and the second dielectric layer to electrically connect the conductive layers.
摘要翻译：提供了装置和方法。浮动栅存储器单元和NAND存储器阵列的选择栅极通过各向异性地去除设置在第一导电层上的第二导电层的部分同时形成，使得第二导电层的剩余部分与第一导电层的侧壁对准并设置在第一导电层的侧壁上导电层。第一导电层设置在设置在基板上的第一介电层上。第二介电层形成在第一导电层和第二导电层的其余部分之上。在第二电介质层上形成第三导电层。在第三导电层上形成第四导电层。对于选择栅极，第四导电层还穿过第三导电层和第二介电层以电连接导电层。

7. 发明授权

US07276733B2 Select lines for NAND memory devices 有权
标题翻译：选择NAND存储器件的线
公开(公告)号：US07276733B2
公开(公告)日：2007-10-02
申请号：US11191505
申请日：2005-07-28
申请人： Michael Violette
发明人： Michael Violette
IPC分类号： H01L27/108 , H01L29/04 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L21/28273
摘要： A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the plurality of NAND strings and the select line. The select line further includes first and second conductive layers separated by a dielectric layer, and a contact that extends from a third conductive layer, disposed on the second conductive layer, to the first conductive layer. The contact is formed in a hole that passes through the second conductive layer and the dielectric layer and that terminates at the first conductive layer. The contact electrically connects the first and second conductive layers. The hole can have a slot shape so that the contact spans two or more NAND strings of the plurality of NAND strings.
摘要翻译： NAND存储器阵列具有耦合到存储器阵列的存储器单元的多个NAND串中的每一个的选择线。选择线在多个NAND串和选择线之一的每个交叉处具有选择栅极。选择线还包括由电介质层分隔的第一和第二导电层，以及从设置在第二导电层上的第三导电层延伸到第一导电层的接触。接触形成在穿过第二导电层和介电层并终止于第一导电层的孔中。接触件电连接第一和第二导电层。孔可以具有槽形状，使得接触跨越多个NAND串中的两个或更多个NAND串。

8. 发明申请

US20050202622A1 Interconnecting conductive layers of memory devices 有权
标题翻译：互连存储器件的导电层
公开(公告)号：US20050202622A1
公开(公告)日：2005-09-15
申请号：US11007138
申请日：2004-12-07
申请人： Michael Violette , Mark Helm
发明人： Michael Violette , Mark Helm
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/8238
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11543
摘要： Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap is disposed on either side of the first and second conductive layers. Each strap electrically interconnects the first and second conductive layers.
摘要翻译：场效应晶体管，选择栅极和选择线具有由层间介电层分离的第一和第二导电层。导电带设置在第一和第二导电层的任一侧上。每个带子电连接第一和第二导电层。

9. 发明申请

US20050130380A1 Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level 审中-公开
标题翻译：半导体器件结构包括金属硅化物互连和基本上相同制造水平的电介质层
公开(公告)号：US20050130380A1
公开(公告)日：2005-06-16
申请号：US11051220
申请日：2005-02-04
申请人： Sanh Tang , Michael Violette
发明人： Sanh Tang , Michael Violette
IPC分类号： G01R31/36 , H01L21/768 , H01L23/535 , H01L21/336
CPC分类号： G01R31/3648 , G01R31/378 , H01L21/28518 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a metal silicide interconnect structure and a dielectric layer that are located at substantially the same fabrication level. The metal silicide interconnect and dielectric layer may be fabricated by forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure.
摘要翻译：半导体器件包括金属硅化物互连结构和位于基本上相同制造水平的介电层。可以通过在包括至少一个栅极结构的衬底上形成非晶或多晶硅层来制造金属硅化物互连和电介质层，在硅层上形成氮化硅层，去除氮化硅层的一部分，去除硅氮化物层的剩余部分，任选地去除氧化硅层，在所得结构上形成金属层，在包含氮气的气氛中退火金属层，并去除任何金属氮化物区域。局部金属硅化物互连结构可以覆盖至少一个栅极结构。

10. 发明申请

US20050106795A1 Methods of forming field effect transistors and methods of forming field effect transistor gates and gate lines 有权
标题翻译：形成场效应晶体管的方法和形成场效应晶体管栅极和栅极线的方法
公开(公告)号：US20050106795A1
公开(公告)日：2005-05-19
申请号：US11000809
申请日：2004-11-30
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： G06K19/07 , H01L21/336 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

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