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1. 发明授权

US06779049B2 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism 有权
标题翻译：具有附加处理单元的对称多处理系统能够访问共享存储器而不在结构上配置地址转换机制
公开(公告)号：US06779049B2
公开(公告)日：2004-08-17
申请号：US09736585
申请日：2000-12-14
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1328
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

2. 发明授权

US06907477B2 Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors 失效
标题翻译：使用DMAC的对称多处理系统允许连接的处理器进行地址转换
公开(公告)号：US06907477B2
公开(公告)日：2005-06-14
申请号：US10782044
申请日：2004-02-19
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/28 , G06F9/28 , G06F13/368
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

3. 发明授权

US06970982B2 Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions 失效
标题翻译：通过广播TLB无效输入指令来在多处理器系统中维持一致性的方法和系统
公开(公告)号：US06970982B2
公开(公告)日：2005-11-29
申请号：US10676540
申请日：2003-10-01
申请人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

4. 发明授权

US07509457B2 Non-homogeneous multi-processor system with shared memory 失效
标题翻译：具有共享内存的非均匀多处理器系统
公开(公告)号：US07509457B2
公开(公告)日：2009-03-24
申请号：US11065537
申请日：2005-02-24
申请人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
发明人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
IPC分类号： G06F12/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

5. 发明申请

US20080162877A1 Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
标题翻译：具有共享内存的非均匀多处理器系统
公开(公告)号：US20080162877A1
公开(公告)日：2008-07-03
申请号：US12049324
申请日：2008-03-15
申请人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
发明人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： H04L63/168 , H04L67/10
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

6. 发明授权

US07233998B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07233998B2
公开(公告)日：2007-06-19
申请号：US09816004
申请日：2001-03-22
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

7. 发明授权

US08032849B2 Integrated circuit chip with modular design 失效
标题翻译：集成电路芯片采用模块化设计
公开(公告)号：US08032849B2
公开(公告)日：2011-10-04
申请号：US12130268
申请日：2008-05-30
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

8. 发明授权

US07114035B2 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US07114035B2
公开(公告)日：2006-09-26
申请号：US10655365
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

9. 发明授权

US07720982B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07720982B2
公开(公告)日：2010-05-18
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

10. 发明授权

US07496673B2 SIMD-RISC microprocessor architecture 失效
标题翻译： SIMD-RISC微处理器架构
公开(公告)号：US07496673B2
公开(公告)日：2009-02-24
申请号：US11065707
申请日：2005-02-24
申请人： Michael Karl Gschwind , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle
发明人： Michael Karl Gschwind , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

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