专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08615745B2 Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
标题翻译：使用解码时间指令优化编译用于增强应用二进制接口（ABI）的代码
公开(公告)号：US08615745B2
公开(公告)日：2013-12-24
申请号：US13251798
申请日：2011-10-03
申请人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

2. 发明申请

US20080065861A1 Method And Apparatus To Extend The Number Of Instruction Bits In Processors With Fixed Length Instructions, In A Manner Compatible With Existing Code 有权
标题翻译：使用固定长度指令扩展处理器中指令位数的方法和装置，与现有代码兼容
公开(公告)号：US20080065861A1
公开(公告)日：2008-03-13
申请号：US11931815
申请日：2007-10-31
申请人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Michael Gschwind , David Luick , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

3. 发明申请

US20070260855A1 Method and apparatus for the dynamic creation of instructions utilizing a wide datapath 有权
标题翻译：用于使用宽数据路径动态创建指令的方法和装置
公开(公告)号：US20070260855A1
公开(公告)日：2007-11-08
申请号：US11416421
申请日：2006-05-02
申请人： Michael Gschwind , Balaram Sinharoy
发明人： Michael Gschwind , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3013 , G06F9/30149 , G06F9/3017 , G06F9/30196 , G06F9/382 , G06F9/384 , G06F9/3861
摘要： A processing system and method includes a predecoder configured to identify instructions that are combinable. Instruction storage is configured to merge instructions that are combinable by replacing the combinable instructions with a wide data internal instruction for execution. An instruction execution unit is configured to execute the internal instruction on a wide datapath.
摘要翻译：一种处理系统和方法包括：预解码器，被配置为识别可组合的指令。指令存储被配置为通过用可执行的宽数据内部指令替换可组合指令来合并可组合的指令。指令执行单元被配置为在宽数据路径上执行内部指令。

4. 发明申请

US20070233766A1 SYSTEM AND METHOD FOR COMPILING SCALAR CODE FOR A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) EXECUTION ENGINE 失效
标题翻译：用于编译单个指令多个数据（SIMD）执行发动机的标量代码的系统和方法
公开(公告)号：US20070233766A1
公开(公告)日：2007-10-04
申请号：US11278639
申请日：2006-04-04
申请人： MICHAEL GSCHWIND
发明人： MICHAEL GSCHWIND
IPC分类号： G06F7/38
CPC分类号： G06F9/3013 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/3885 , G06F9/3887
摘要： A system, method, and computer program product are provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.
摘要翻译：提供了一种用于使用SIMD数据并行执行单元执行标量操作的系统，方法和计算机程序产品。利用说明性实施例的机制，识别可以使用SIMD数据并行执行单元中的向量操作来执行应用代码中的标量运算。标量运算例如通过静态或动态编译器被转换成一个或多个向量加载指令和一个或多个向量计算指令。此外，可以生成控制字以使用向量加载指令调整加载了这些标量值的向量寄存器内的标量运算的标量值的对齐。用于调整向量寄存器内的标量值的对准量可以是静态或动态地确定的。

5. 发明申请

US20070192545A1 Low complexity speculative multithreading system based on unmodified microprocessor core 失效
标题翻译：基于未修改的微处理器核心的低复杂度推测性多线程系统
公开(公告)号：US20070192545A1
公开(公告)日：2007-08-16
申请号：US11351830
申请日：2006-02-10
申请人： Alan Gara , Michael Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Gschwind , Valentina Salapura
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

6. 发明申请

US20070038848A1 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US20070038848A1
公开(公告)日：2007-02-15
申请号：US11446020
申请日：2006-06-02
申请人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
发明人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/44
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。固定宽度指令包括不连续的寄存器说明符。

7. 发明申请

US20060236036A1 Method and apparatus for predictive scheduling of memory accesses based on reference locality 审中-公开
标题翻译：基于参考位置的存储器访问预测调度的方法和装置
公开(公告)号：US20060236036A1
公开(公告)日：2006-10-19
申请号：US11105058
申请日：2005-04-13
申请人： Michael Gschwind , Jude Rivers , John-David Wellman , Victor Zyuban
发明人： Michael Gschwind , Jude Rivers , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： There are provided methods and apparatus for accessing a memory array. A method for accessing a memory array includes the step of predicting whether at least two memory references can be satisfied by a single array access based on one of an instruction address, local instruction history and global instruction history.
摘要翻译：提供了用于访问存储器阵列的方法和装置。一种用于访问存储器阵列的方法包括以下步骤：基于指令地址，本地指令历史和全局指令历史中的一个来预测是否可以通过单个阵列访问来满足至少两个存储器引用。

8. 发明申请

US20060174089A1 Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture 审中-公开
标题翻译：用于将宽指令字嵌入固定长度指令集架构中的方法和装置
公开(公告)号：US20060174089A1
公开(公告)日：2006-08-03
申请号：US11047983
申请日：2005-02-01
申请人： Erik Altman , Michael Gschwind , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Daniel Prener , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F15/00
CPC分类号： G06F9/30185 , G06F9/30072 , G06F9/30076 , G06F9/30145 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/382 , G06F9/3822
摘要： A method, system, and computer program product for mixing of conventional and augmented instructions within an instruction stream, wherein control may be directly transferred, without operating system intervention, between one type of instruction to another. Extra instruction word bits are added in a manner that is designed to minimally interfere with the encoding, decoding, and instruction processing environment in a manner compatible with existing conventional fixed instruction width code. A plurality of instruction words are inserted into an instruction word oriented architecture to form an encoding group of instruction words. The instruction words in the encoding group are dispatched and executed either independently or in parallel based on a specific microprocessor implementation. The encoding group does not indicate any form of required parallelism or sequentiality. One or more indicators for the encoding group are created, wherein one indicator is used to indicate presence of the encoding group.
摘要翻译：一种用于在指令流内混合常规和增强指令的方法，系统和计算机程序产品，其中可以在一种类型的指令与另一种指令之间直接传送控制，而无需操作系统干预。附加指令字位以被设计为以与现有常规固定指令宽度代码兼容的方式最小程度地干扰编码，解码和指令处理环境的方式被添加。多个指令字被插入到面向指令字的架构中以形成指令字的编码组。基于特定的微处理器实现，编码组中的指令字被独立地或并行地调度和执行。编码组不表示任何形式的必需的并行性或顺序性。创建编码组的一个或多个指示符，其中一个指示符用于指示编码组的存在。

9. 发明申请

US20050216675A1 Method and apparatus for directory-based coherence with distributed directory management 有权
标题翻译：基于目录的分布式目录管理一致性的方法和装置
公开(公告)号：US20050216675A1
公开(公告)日：2005-09-29
申请号：US10809581
申请日：2004-03-25
申请人： Michael Gschwind , Charles Johns , Thoung Truong
发明人： Michael Gschwind , Charles Johns , Thoung Truong
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0824
摘要： The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Buffers are interconnected to processor memory and a plurality of processor elements, each element interconnected to different buffers. Cache lines are requested from memory, and the requests, responses, and detections therein are available for particular access modes, therein providing additional coherence of the data. Processing of the directory data is performed by processing elements.
摘要翻译：本发明提供了一种并行处理架构，其中多个处理器可以访问共享存储器层级。存储器层次结构级别具有一致性目录和相关联的目录数据，其中多个高速缓存行各自与不同的数据相关联。缓冲器互连到处理器存储器和多个处理器元件，每个元件互连到不同的缓冲器。从存储器请求高速缓存行，并且其中的请求，响应和检测可用于特定访问模式，其中提供数据的附加一致性。目录数据的处理由处理元素执行。

10. 发明申请

US20050216672A1 Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches 有权
标题翻译：使用预取缓存的基于目录的一致性分布式目录管理的方法和装置
公开(公告)号：US20050216672A1
公开(公告)日：2005-09-29
申请号：US10809579
申请日：2004-03-25
申请人： Michael Gschwind , Charles Johns , Thoung Truong
发明人： Michael Gschwind , Charles Johns , Thoung Truong
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0817
摘要： The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Prefetch caches are interconnected to processor memory and a plurality of processor elements, each element interconnected to different buffers. Cache lines are requested from memory, and the requests, responses, and detections therein are available for particular access modes, therein providing additional coherence of the data. Processing of said directory data is performed by processing elements. In one embodiment, the system comprises an integrated prefetch cache.
摘要翻译：本发明提供了一种并行处理架构，其中多个处理器可以访问共享存储器层级。存储器层次结构级别具有一致性目录和相关联的目录数据，其中多个高速缓存行各自与不同的数据相关联。预取高速缓存被互连到处理器存储器和多个处理器元件，每个元件互连到不同的缓冲器。从存储器请求高速缓存行，并且其中的请求，响应和检测可用于特定访问模式，其中提供数据的附加一致性。所述目录数据的处理由处理元素执行。在一个实施例中，系统包括集成预取高速缓存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式