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1. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

2. 发明授权

US06315637B1 Photoresist removal using a polishing tool 有权
标题翻译：使用抛光工具去除光刻胶
公开(公告)号：US06315637B1
公开(公告)日：2001-11-13
申请号：US09484601
申请日：2000-01-18
申请人： Eric M. Apelgren , Jonathan B. Smith , Paul R. Besser
发明人： Eric M. Apelgren , Jonathan B. Smith , Paul R. Besser
IPC分类号： B24B100
CPC分类号： H01L21/31058 , B24B37/042
摘要： The present invention is directed to semiconductor processing operations. In one illustrative embodiment, the invention comprises providing a wafer having a layer of photoresist formed thereabove, positioning the layer of photoresist in contact with a polishing pad or a polishing tool, and rotating at least one of the wafer and the polishing pad to remove substantially all of the layers of photoresist.
摘要翻译：本发明涉及半导体处理操作。在一个说明性实施例中，本发明包括提供具有在其上形成的光致抗蚀剂层的晶片，将光致抗蚀剂层定位成与抛光垫或抛光工具接触，并且旋转晶片和抛光垫中的至少一个，以基本上去除所有的光刻胶层。

3. 发明授权

US06261963B1 Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices 有权
标题翻译：阻挡金属层反向电镀以提高铜互连器件的电迁移性能
公开(公告)号：US06261963B1
公开(公告)日：2001-07-17
申请号：US09611729
申请日：2000-07-07
申请人： Larry Zhao , Paul R. Besser , Eric M. Apelgren , Christian Zistl , Jonathan B. Smith
发明人： Larry Zhao , Paul R. Besser , Eric M. Apelgren , Christian Zistl , Jonathan B. Smith
IPC分类号： H01L21302
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76829 , H01L21/76835 , H01L21/7684 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S438/927
摘要： A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.
摘要翻译：提供了一种用于形成导电互连的方法，所述方法包括在结构层上形成第一介电层，在第一介电层中形成第一开口，并在第一开口中形成第一导电结构。该方法还包括在第一介电层之上和第一导电结构之上形成第二电介质层，在第二导电结构的至少一部分上方的第二电介质层中形成第二开口，第二开口具有侧表面和并且在侧表面和底表面上的第二开口中形成至少一个阻挡金属层。此外，该方法包括从底表面去除至少一个阻挡金属层的一部分，以及在第二开口中形成第二导电结构，第二导电结构与第一导电结构的至少一部分接触。该方法还包括通过使第二导电结构和第一导电结构退火来形成导电互连。

4. 发明授权

US07737021B1 Resist trim process to define small openings in dielectric layers 有权
标题翻译：抵抗修整过程以限定电介质层中的小开口
公开(公告)号：US07737021B1
公开(公告)日：2010-06-15
申请号：US10261613
申请日：2002-09-30
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料。

5. 发明授权

US06514844B1 Sidewall treatment for low dielectric constant (low K) materials by ion implantation 失效
标题翻译：通过离子注入对低介电常数（低K）材料进行侧壁处理
公开(公告)号：US06514844B1
公开(公告)日：2003-02-04
申请号：US09840598
申请日：2001-04-23
申请人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
发明人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
IPC分类号： H01L2144
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76877
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.
摘要翻译：提供了一种方法，该方法包括形成第一导电结构，以及在第一导电结构之上形成第一电介质层。该方法还包括在第一导电结构的至少一部分上方致密化第一电介质层的一部分，以及在第一介电层的致密部分中形成第一开口。

6. 发明授权

US06500755B2 Resist trim process to define small openings in dielectric layers 有权
标题翻译：抵抗修整过程以限定电介质层中的小开口
公开(公告)号：US06500755B2
公开(公告)日：2002-12-31
申请号：US09731577
申请日：2000-12-06
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料。

7. 发明授权

US06610594B2 Locally increasing sidewall density by ion implantation 有权
公开(公告)号：US06610594B2
公开(公告)日：2003-08-26
申请号：US09902024
申请日：2001-07-10
申请人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
发明人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76802 , H01L21/7681 , H01L21/76828 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

8. 发明授权

US06313538B1 Semiconductor device with partial passivation layer 有权
标题翻译：具有部分钝化层的半导体器件
公开(公告)号：US06313538B1
公开(公告)日：2001-11-06
申请号：US09489479
申请日：2000-01-21
申请人： Christian Zistl , Paul R. Besser , Eric M. Apelgren , Nicholas J. Kepler , Srikanteswara Dakshina-Murthy
发明人： Christian Zistl , Paul R. Besser , Eric M. Apelgren , Nicholas J. Kepler , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76834 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.
摘要翻译：半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层。一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质并且与钝化层和第一介电层接触。

9. 发明授权

US5780861A Adjustable blade reticle assembly 失效
标题翻译：可调节刀片光罩组件
公开(公告)号：US5780861A
公开(公告)日：1998-07-14
申请号：US756494
申请日：1996-11-26
申请人： Eric M. Apelgren , Darrell A. Harris
发明人： Eric M. Apelgren , Darrell A. Harris
IPC分类号： G03F1/00 , G03F1/64 , G03F7/20 , G21K5/00
CPC分类号： G03F7/70866 , G03F1/64 , G03F7/70066
摘要： Apparatus and method for inhibiting the image of a transparent, undesired feature on a reticle from printing on semiconductor material. The apparatus includes a frame attachment connected to a pellicle frame that is attached to a reticle. A blade that is opaque to ultraviolet light is moveable across the frame attachment and may be positioned proximate the undesired feature of the reticle to prevent the printing of the image of the undesired feature on the semiconductor material. The blade may be positioned above the undesired feature to inhibit ultraviolet light from an illumination source from impinging upon the undesired feature. Alternatively, the blade may be positioned below the undesired feature to inhibit ultraviolet light passing through the undesired feature from impinging upon the semiconductor material.
摘要翻译：用于抑制在半导体材料上印刷的掩模版上的透明的，不期望的特征的图像的装置和方法。该装置包括连接到防护薄膜组件框架的框架附件，该防护薄膜组件框架附接到掩模版。对紫外线不透明的刀片可移动穿过框架附件，并且可以靠近掩模版的不期望的特征定位，以防止在半导体材料上打印不期望的特征的图像。刀片可以位于不需要的特征之上，以防止来自照明源的紫外线撞击不期望的特征。或者，刀片可以位于不需要的特征之下，以抑制穿过不需要的特征的紫外光照射到半导体材料上。

10. 发明授权

US5848382A Method for automated energy dose measurement and adjustment for a photoaligner 失效
标题翻译：自动能量测量和光电子标记器调整方法
公开(公告)号：US5848382A
公开(公告)日：1998-12-08
申请号：US884522
申请日：1997-06-27
申请人： Eric M. Apelgren , Gerald W. Barnett
发明人： Eric M. Apelgren , Gerald W. Barnett
IPC分类号： G03F7/20 , G01C25/00
CPC分类号： G03F7/70525 , G03F7/70558
摘要： A Visual Basic software program to automate the procedures required for energy dose verification and adjustment of the ASM photoaligner. The software program has the capability of manipulating the ASM photoaligner through a resident software routine of the photoaligner. In addition, the software program has a user interface which prompts the operator for inputs and instructs the operator on what is required to perform the energy dose calibration. This ensures a reproducible procedure regardless of the photoaligner being tested or the operator doing the testing. Automating this procedure allows changing the photoaligner energy dose through the ASM Machine Constants (values stored in the ASM photoaligner that control the operation of the photoaligner). If the input data is out of specification the program will either reference a trouble shooting guide or request that the specific procedure be repeated for verification. After collecting the data from the operator, the program makes the necessary calculations and compares the results to a predefined data base which contains the specification limits for each of the individual photoaligners. Besides saving time, automating these procedures ensures that all operators perform them the same way, thereby eliminating operator-to-operator variation. Furthermore, it will no longer be necessary to open the ASM electronics cabinet to adjust the shutter control board potentiometer for brining the dose back to specification and by making the changes through software it will be possible to track them over time.
摘要翻译：一个Visual Basic软件程序，用于自动化能量剂量验证和调整ASM光电位器所需的程序。该软件程序可以通过光标签器的驻留软件程序来操纵ASM光标签器。此外，该软件程序具有一个用户界面，它提示操作员进行输入，并指示操作人员执行能量剂量校准所需要的。无论正在测试的光电子标记或操作人员进行测试，都可确保可重现的程序。自动执行此过程允许通过ASM机器常数（存储在控制光电加工者操作的ASM光电位器中存储的值）更改光电子能量的剂量。如果输入数据超出规格，程序将参考故障排除指南或要求重复具体步骤进行验证。在从运营商收集数据之后，程序进行必要的计算，并将结果与预定义的数据库进行比较，该数据库包含每个单独光电位器的规范限制。除了节省时间，自动化这些程序可以确保所有操作员以相同的方式执行它们，从而消除操作员与操作者之间的差异。此外，不再需要打开ASM电子柜来调整快门控制板电位器，以便将剂量恢复到规格，并通过软件进行更改，以便随时间跟踪它们。

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