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1. 发明授权

US06433372B1 Dense multi-gated device design 失效
标题翻译：密集的多门控设备设计
公开(公告)号：US06433372B1
公开(公告)日：2002-08-13
申请号：US09527863
申请日：2000-03-17
申请人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
发明人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H01L2972
CPC分类号： H01L29/66484
摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.
摘要翻译：具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。

2. 发明授权

US06580293B1 Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
标题翻译：身体接触和双门接触差分逻辑电路及其操作方法
公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译：设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

3. 发明授权

US06577178B1 Transient gate tunneling current control 有权
标题翻译：瞬态栅极隧道电流控制
公开(公告)号：US06577178B1
公开(公告)日：2003-06-10
申请号：US10064504
申请日：2002-07-23
申请人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
发明人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
IPC分类号： H03K1730
CPC分类号： H03K19/00361 , H03K19/0948
摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.
摘要翻译：电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。此外，第一组晶体管和第二组晶体管共享公共输入和输出。第一组晶体管表现出比第二组晶体管更高的隧穿电流。第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

4. 发明授权

US06191628B1 Circuit for controlling the slew rate of a digital signal 失效
标题翻译：用于控制数字信号的转换速率的电路
公开(公告)号：US06191628B1
公开(公告)日：2001-02-20
申请号：US09224763
申请日：1999-01-04
申请人： Kerry Bernstein , Edward J. Nowak , Norman J. Rohrer
发明人： Kerry Bernstein , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H03K512
CPC分类号： H03K19/00323 , H03K5/131 , H03K5/133 , H03K19/00361 , H03K2005/00071
摘要： A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.
摘要翻译：用于选择性地控制数据线上的信号的转换速率的电路。电容器一端连接到电源的公共端子和开关电路。开关电路有利地将电容器响应于控制脉冲连接到数据线，电容性地加载数据线，使得转换速率降低。当控制脉冲处于不同状态时，电容器通过开关电路连接到电源的端子，并用作去耦电容器。电容器的双重作用通过利用两个功能中的一个组件来提供有效的电路布局。

5. 发明授权

US08492214B2 Damascene metal gate and shield structure, methods of manufacture and design structures 有权
标题翻译：大马士革金属门和屏蔽结构，制造和设计结构的方法
公开(公告)号：US08492214B2
公开(公告)日：2013-07-23
申请号：US13051510
申请日：2011-03-18
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/338
CPC分类号： H01L31/0232 , G06F17/5045 , G06F17/5054 , H01L27/14632 , H01L27/14683 , H01L29/66545
摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.
摘要翻译：提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。该方法包括在虚拟栅极结构上形成介电层。该方法还包括在电介质层中形成一个或多个凹槽。该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

6. 发明申请

US20120181588A1 PIXEL SENSOR CELLS WITH A SPLIT-DIELECTRIC TRANSFER GATE 失效
标题翻译：具有分离电介质转移栅的像素传感器电池
公开(公告)号：US20120181588A1
公开(公告)日：2012-07-19
申请号：US13005650
申请日：2011-01-13
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/113 , G06F17/50 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14689
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.
摘要翻译：像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。

7. 发明授权

US07790611B2 Method for FEOL and BEOL wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US07790611B2
公开(公告)日：2010-09-07
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

8. 发明申请

US20090101978A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

9. 发明申请

US20090065834A1 IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS 有权
标题翻译：具有电动活性光学元件的图像
公开(公告)号：US20090065834A1
公开(公告)日：2009-03-12
申请号：US11850798
申请日：2007-09-06
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L27/146
CPC分类号： H01L27/14636 , H01L27/14625
摘要： A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.
摘要翻译：一种包括有源像素单元阵列的CMOS图像传感器。每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。形成的透光导线结构提供电和光学功能。通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。用于导线层的电气功能包括用作电容器板，电阻器或互连件。

10. 发明申请

US20080284021A1 Method for FEOL and BEOL Wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US20080284021A1
公开(公告)日：2008-11-20
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

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