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1. 发明授权

US06874133B2 Integrated circuit design layout compaction method 有权
标题翻译：集成电路设计布局压实方法
公开(公告)号：US06874133B2
公开(公告)日：2005-03-29
申请号：US10309958
申请日：2002-12-04
申请人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
发明人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.
摘要翻译：多个构件装置被限定在具有一对间隔开的平行侧面的保形轮廓中。与每个成员设备相关联的是间距约束，其设定成员设备与另一个成员设备和保形轮廓的每一侧间隔的最小距离。根据需要增加和/或减小构件装置和/或共形轮廓的侧面之间的间隔，以使成员装置接收的保形轮廓的面积最小化，而不违反间隔约束，同时从保形轮廓排除其中定义的任何非成员设备的全部或部分。

2. 发明授权

US07093220B2 Method for generating constrained component placement for integrated circuits and packages 有权
标题翻译：用于为集成电路和封装生成受限元件放置的方法
公开(公告)号：US07093220B2
公开(公告)日：2006-08-15
申请号：US10674085
申请日：2003-09-29
申请人： Elias Fallon , Rob A. Rutenbar
发明人： Elias Fallon , Rob A. Rutenbar
IPC分类号： G06F9/45
CPC分类号： G06F17/5072
摘要： A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component tagged for symmetric placement on both sides of a symmetry line; performing at least one search of the tree structure to determine an initial placement of a subset of the components; and performing another search of the tree structure to determine a final placement of the subset of components whereupon at least a part of each component tagged for symmetric placement is positioned on each side of the symmetry line. The method can be embodied as instructions stored on a computer readable medium which, when executed by a processor, cause the processor to implement the method.
摘要翻译：一种用于确定电路中的部件放置的方法包括：形成树结构，该树结构定义了在对称线的第一侧，第二侧或两侧上与树结构相关联的多个部件中的每一个的布置，至少具有在对称线的两侧标记为对称放置的一个部件; 执行所述树结构的至少一次搜索以确定所述组件的子集的初始放置; 以及执行树结构的另一搜索以确定组件子集的最终放置，因此为对称放置标记的每个组件的至少一部分位于对称线的每一侧上。该方法可以被实现为存储在计算机可读介质上的指令，当由处理器执行时，其使得处理器实现该方法。

3. 发明授权

US08639510B1 Acoustic scoring unit implemented on a single FPGA or ASIC 失效
标题翻译：声学评分单元在单个FPGA或ASIC上实现
公开(公告)号：US08639510B1
公开(公告)日：2014-01-28
申请号：US12341160
申请日：2008-12-22
申请人： Kai Yu , Rob A. Rutenbar
发明人： Kai Yu , Rob A. Rutenbar
IPC分类号： G10L15/14 , G10L15/00 , G10L15/18
CPC分类号： G10L15/08 , G10L15/32 , G10L2015/025 , G10L2015/085
摘要： A hardware acoustic scoring unit for a speech recognition system and a method of operation thereof are provided. Rather than scoring all senones in an acoustic model used for the speech recognition system, acoustic scoring logic first scores a set of ciphones based on acoustic features for one frame of sampled speech. The acoustic scoring logic then scores senones associated with the N highest scored ciphones. In one embodiment, the number (N) is three. While the acoustic scoring logic scores the senones associated with the N highest scored ciphones, high score ciphone identification logic operates in parallel with the acoustic scoring unit to identify one or more additional ciphones that have scores greater than a threshold. Once the acoustic scoring unit finishes scoring the senones for the N highest scored ciphones, the acoustic scoring unit then scores senones associated with the one or more additional ciphones.
摘要翻译：提供了一种用于语音识别系统的硬件声学评分单元及其操作方法。声学评分逻辑不是在用于语音识别系统的声学模型中对所有的声音进行评分，而是首先根据一帧采样语音的声学特征对一组虹吸进行评分。声学评分逻辑然后评分与N个最高得分的虹吸管相关联的声调。在一个实施例中，数（N）为3。虽然声学评分逻辑评分与N个最高得分的虹吸管相关联的声音，但高分数人声识别逻辑与声学评分单元并行操作，以识别具有大于阈值的分数的一个或多个附加虹吸。一旦声学评分单元完成对N个最高得分的虹吸分数的声分数，则声学评分单元然后评分与一个或多个附加虹吸管相关联的声调。

4. 发明授权

US08463610B1 Hardware-implemented scalable modular engine for low-power speech recognition 失效
标题翻译：硬件实现的可扩展模块化引擎，用于低功耗语音识别
公开(公告)号：US08463610B1
公开(公告)日：2013-06-11
申请号：US12355973
申请日：2009-01-19
申请人： Patrick J. Bourke , Rob A. Rutenbar
发明人： Patrick J. Bourke , Rob A. Rutenbar
IPC分类号： G10L15/00 , G10L15/18
CPC分类号： G10L15/197 , G06N7/005 , G10L15/285
摘要： The present invention relates to a low-power speech recognition system. In one embodiment, the speech recognition system is implemented in hardware and includes a backend search engine that operates to recognize words based on senone scores provided by an acoustic scoring stage. The backend search engine includes a scoring engine, a transition engine, and a language model engine. For a frame of sampled speech, the scoring engine reads active acoustic unit models from external memory, updates the active acoustic unit models based on corresponding senone scores received from an acoustic scoring stage, and writes the active acoustic unit models back to the external memory. The scoring engine enters a low-power state until processing for a next frame of sampled speech is to begin. The transition stage identifies any completed words, and the language model engine processes completed words to identify words that are likely to follow in a subsequent frame.
摘要翻译：本发明涉及一种低功率语音识别系统。在一个实施例中，语音识别系统以硬件实现，并且包括后端搜索引擎，其操作以基于由声学评分级提供的语音分数来识别单词。后端搜索引擎包括评分引擎，转换引擎和语言模型引擎。对于采样语音的帧，评分引擎从外部存储器读取有效的声学单元模型，基于从声学评分级接收到的相应的音调分数来更新主动声学单元模型，并将有源声学单元模型写回外部存储器。评分引擎进入低功率状态，直到下一帧采样语音的处理开始。过渡阶段识别任何已完成的单词，并且语言模型引擎处理完成的单词以识别在随后的框架中可能遵循的单词。

5. 发明授权

US07920992B2 Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes 失效
标题翻译：用于对集成电路，系统和制造过程中的不确定性进行建模的方法和系统
公开(公告)号：US07920992B2
公开(公告)日：2011-04-05
申请号：US11370711
申请日：2006-03-08
申请人： Rob A. Rutenbar , James D. Ma , Claire F. Fang , Amith Singhee
发明人： Rob A. Rutenbar , James D. Ma , Claire F. Fang , Amith Singhee
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： A method and system for modeling uncertainties in integrated circuits, systems and fabrication processes may include defining interval values for each uncertain component or parameter in a circuit or system. The method may also include replacing scalar operations with interval operations in an algorithm and discontinuing interval operations in the algorithm in response to a predetermined condition. The method may also include generating a plurality of scalar samples from a plurality of intervals and determine a distribution of each uncertain component or parameter from the scalar samples of the intervals.
摘要翻译：用于对集成电路，系统和制造过程中的不确定性进行建模的方法和系统可以包括为电路或系统中的每个不确定分量或参数定义间隔值。该方法还可以包括用算法中的间隔操作来替换标量运算，并响应于预定条件在算法中停止间隔操作。该方法还可以包括从多个间隔生成多个标量样本，并根据间隔的标量样本确定每个不确定分量或参数的分布。

6. 发明授权

US07058916B2 Method for automatically sizing and biasing circuits by means of a database 失效
标题翻译：通过数据库自动调整和偏置电路的方法
公开(公告)号：US07058916B2
公开(公告)日：2006-06-06
申请号：US10174395
申请日：2002-06-18
申请人： Rodney Phelps , Ronald A. Rohrer , Anthony J. Gadient , Rob A. Rutenbar , L. Richard Carley
发明人： Rodney Phelps , Ronald A. Rohrer , Anthony J. Gadient , Rob A. Rutenbar , L. Richard Carley
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.
摘要翻译：在自动调整和偏置电路的方法中，提供数据库，其包括与可用于形成集成电路的单元有关的多个记录。选择电路单元的单元参数，并将其与存储在数据库中的记录中的单元参数进行比较。基于该比较选择数据库中的一个记录，并且根据该记录确定电路的性能特性。

7. 发明授权

US06918102B2 Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout 有权
标题翻译：用于在半导体电路布局中精确地相对定位器件的方法和装置
公开(公告)号：US06918102B2
公开(公告)日：2005-07-12
申请号：US10338311
申请日：2003-01-08
申请人： Rob A. Rutenbar , Regis R. Colwell , Elias L. Fallon
发明人： Rob A. Rutenbar , Regis R. Colwell , Elias L. Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.
摘要翻译：确定电路布局中的设备的位置的方法包括定义单元阵列并且定义阵列中的多个设备轮廓，每个设备轮廓在至少一个单元中接收。建立一组大小约束，表示每个设备的大小。对于每列具有完整包含多个器件轮廓的每个单元格的单元格行，确定其中一个器件轮廓的位置，并且为每个其他器件轮廓建立约束，该轮廓表示其相对于该位置的位置的位置设备大纲。建立每对相邻设备轮廓的间隔约束，其间表示间隔。同时解决上述约束，并根据解决方案生成设备轮廓的布局。

8. 发明授权

US08352265B1 Hardware implemented backend search engine for a high-rate speech recognition system 失效
标题翻译：硬件实现了高速率语音识别系统的后端搜索引擎
公开(公告)号：US08352265B1
公开(公告)日：2013-01-08
申请号：US12341640
申请日：2008-12-22
申请人： Edward Lin , Rob A. Rutenbar
发明人： Edward Lin , Rob A. Rutenbar
IPC分类号： G10L15/14 , G10L15/00 , G10L15/18
CPC分类号： G10L15/34 , G06N7/005 , G10L15/142 , G10L15/197 , G10L2015/022
摘要： A hardware implemented backend search stage, or engine, for a speech recognition system is provided. In one embodiment, the backend search engine includes a number of pipelined stages including a fetch stage, an updating stage which may be a Viterbi stage, a transition and prune stage, and a language model stage. Each active triphone of each active word is represented by a corresponding triphone model. By being pipelined, the stages of the backend search engine are enabled to simultaneously process different triphone models, thereby providing high-rate backend searching for the speech recognition system. In one embodiment, caches may be used to cache frequently and/or recently accessed triphone information utilized by the fetch stage, frequently and/or recently accessed triphone-to-senone mappings utilized by the updating stage, or both.
摘要翻译：提供了用于语音识别系统的硬件实现的后端搜索阶段或引擎。在一个实施例中，后端搜索引擎包括多个流水线阶段，包括获取阶段，可以是维特比阶段的更新阶段，过渡和修剪阶段以及语言模型阶段。每个活动字的每个活动三角形由相应的三电话模型表示。通过流水线化，后端搜索引擎的阶段能够同时处理不同的三音箱模型，从而为语音识别系统提供高速后端搜索。在一个实施例中，高速缓存可用于缓存由获取级利用的经常和/或最近访问的三进制信息信息，由更新阶段或两者使用的经常和/或最近访问的三进制对话音映射。

9. 发明授权

US08290761B1 Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter models 有权
标题翻译：使用压缩参数模型快速建模和模拟集成电路中的管芯内统计变化的方法和装置
公开(公告)号：US08290761B1
公开(公告)日：2012-10-16
申请号：US12478312
申请日：2009-06-04
申请人： Amith Singhee , Sonia Singhal , Rob A. Rutenbar
发明人： Amith Singhee , Sonia Singhal , Rob A. Rutenbar
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method and system for rapidly modeling and simulating intra-die variations in an integrated circuit are disclosed. In one embodiment, each logic gate in an integrated circuit has a characteristic to be simulated, where the characteristic of the gate is a function of one or more parameters having intra-die variations. For each parameter, a model of intra-die variation of the parameter is generated such that a number of random variables in the model is compressed to a reduced number (r) of random variables based on a spatial correlation of the intra-die variation of the parameter. Then, using a Quasi Monte Carlo (QMC) technique, the integrated circuit is simulated based on the model of the intra-die variation of each of the one or more parameters.
摘要翻译：公开了一种用于快速建模和模拟集成电路中的管芯内变化的方法和系统。在一个实施例中，集成电路中的每个逻辑门具有要被模拟的特性，其中栅极的特性是具有管芯内变化的一个或多个参数的函数。对于每个参数，生成参数的模内变化的模型，使得模型中的随机变量的数量基于模内变化的空间相关性被压缩为减少数量（r）的随机变量参数。然后，使用准蒙特卡罗（QMC）技术，基于一个或多个参数中的每一个的管芯内变化的模型来模拟集成电路。

10. 发明授权

US06957400B2 Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design 有权
标题翻译：用于量化电路设计中多个竞争目标的权衡的方法和装置
公开(公告)号：US06957400B2
公开(公告)日：2005-10-18
申请号：US10652018
申请日：2003-08-29
申请人： Hongzhou Liu , Rodney Phelps , Rob A. Rutenbar
发明人： Hongzhou Liu , Rodney Phelps , Rob A. Rutenbar
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is then determined for each allocated design point. From a subset of the allocated design points, a plurality of new design points is generated for the circuit. The cost for each new design point is then determined and each new design point having a cost that is the same or more favorable than the most favorable cost associated with the allocated design points is allocated to the design population. The design points allocated to the design population can then be displayed for selection of one of said allocated design points having desired performances of the circuit.
摘要翻译：为了识别电路设计中的高质量设计点，为电路生成多个设计点。设计点的一部分被分配给设计人员。然后为每个分配的设计点确定成本。从分配的设计点的子集中，为电路生成多个新的设计点。然后确定每个新设计点的成本，并且将具有与分配的设计点相关联的最有利成本相同或更有利的成本的每个新设计点分配给设计人群。然后可以显示分配给设计人口的设计点，以选择具有期望的电路性能的所述分配的设计点之一。

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