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1. 发明授权

US07543262B2 Analog layout module generator and method 有权
标题翻译：模拟布局模块发生器和方法
公开(公告)号：US07543262B2
公开(公告)日：2009-06-02
申请号：US11295268
申请日：2005-12-06
申请人： Zhigang Wang , Elias Fallon , Regis R. Colwell
发明人： Zhigang Wang , Elias Fallon , Regis R. Colwell
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
摘要翻译：在集成电路设计中的设备布局的计算机实现方法中，选择具有多个单元的阵列并将其存储在计算机的存储器中。在计算机的显示器上显示电路的多个互连电路装置的示意图。所显示的示意图的一个或多个电路装置由用户选择。响应于每个电路装置的选择，计算机的处理装置用电路装置的相应布局实例填充计算机的存储器中的阵列的空单元，其中每个布局实例表示材料的物理布置），形成相应的所选择的电路装置。

2. 发明申请

US20050028122A1 Method for generating constrained component placement for integrated circuits and packages 有权
标题翻译：用于为集成电路和封装生成受限元件放置的方法
公开(公告)号：US20050028122A1
公开(公告)日：2005-02-03
申请号：US10674085
申请日：2003-09-29
申请人： Elias Fallon , Rob Rutenbar
发明人： Elias Fallon , Rob Rutenbar
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component tagged for symmetric placement on both sides of a symmetry line; performing at least one search of the tree structure to determine an initial placement of a subset of the components; and performing another search of the tree structure to determine a final placement of the subset of components whereupon at least a part of each component tagged for symmetric placement is positioned on each side of the symmetry line. The method can be embodied as instructions stored on a computer readable medium which, when executed by a processor, cause the processor to implement the method.
摘要翻译：一种用于确定电路中的部件放置的方法包括：形成树结构，该树结构定义了在对称线的第一侧，第二侧或两侧上与树结构相关联的多个部件中的每一个的布置，至少具有在对称线的两侧标记为对称放置的一个部件; 执行所述树结构的至少一次搜索以确定所述组件的子集的初始放置; 以及执行树结构的另一搜索以确定组件子集的最终放置，因此为对称放置标记的每个组件的至少一部分位于对称线的每一侧上。该方法可以被实现为存储在计算机可读介质上的指令，当由处理器执行时，其使得处理器实现该方法。

3. 发明申请

US20070130553A1 Analog layout module generator and method 有权
标题翻译：模拟布局模块发生器和方法
公开(公告)号：US20070130553A1
公开(公告)日：2007-06-07
申请号：US11295268
申请日：2005-12-06
申请人： Zhigang Wang , Elias Fallon , Regis Colwell
发明人： Zhigang Wang , Elias Fallon , Regis Colwell
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
摘要翻译：在集成电路设计中的设备布局的计算机实现方法中，选择具有多个单元的阵列并将其存储在计算机的存储器中。在计算机的显示器上显示电路的多个互连电路装置的示意图。所显示的示意图的一个或多个电路装置由用户选择。响应于每个电路装置的选择，计算机的处理装置用电路装置的相应布局实例填充计算机的存储器中的阵列的空单元，其中每个布局实例表示材料的物理布置），形成相应的所选择的电路装置。

4. 发明授权

US07093220B2 Method for generating constrained component placement for integrated circuits and packages 有权
标题翻译：用于为集成电路和封装生成受限元件放置的方法
公开(公告)号：US07093220B2
公开(公告)日：2006-08-15
申请号：US10674085
申请日：2003-09-29
申请人： Elias Fallon , Rob A. Rutenbar
发明人： Elias Fallon , Rob A. Rutenbar
IPC分类号： G06F9/45
CPC分类号： G06F17/5072
摘要： A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component tagged for symmetric placement on both sides of a symmetry line; performing at least one search of the tree structure to determine an initial placement of a subset of the components; and performing another search of the tree structure to determine a final placement of the subset of components whereupon at least a part of each component tagged for symmetric placement is positioned on each side of the symmetry line. The method can be embodied as instructions stored on a computer readable medium which, when executed by a processor, cause the processor to implement the method.
摘要翻译：一种用于确定电路中的部件放置的方法包括：形成树结构，该树结构定义了在对称线的第一侧，第二侧或两侧上与树结构相关联的多个部件中的每一个的布置，至少具有在对称线的两侧标记为对称放置的一个部件; 执行所述树结构的至少一次搜索以确定所述组件的子集的初始放置; 以及执行树结构的另一搜索以确定组件子集的最终放置，因此为对称放置标记的每个组件的至少一部分位于对称线的每一侧上。该方法可以被实现为存储在计算机可读介质上的指令，当由处理器执行时，其使得处理器实现该方法。

5. 发明授权

US06874133B2 Integrated circuit design layout compaction method 有权
标题翻译：集成电路设计布局压实方法
公开(公告)号：US06874133B2
公开(公告)日：2005-03-29
申请号：US10309958
申请日：2002-12-04
申请人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
发明人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.
摘要翻译：多个构件装置被限定在具有一对间隔开的平行侧面的保形轮廓中。与每个成员设备相关联的是间距约束，其设定成员设备与另一个成员设备和保形轮廓的每一侧间隔的最小距离。根据需要增加和/或减小构件装置和/或共形轮廓的侧面之间的间隔，以使成员装置接收的保形轮廓的面积最小化，而不违反间隔约束，同时从保形轮廓排除其中定义的任何非成员设备的全部或部分。

6. 发明授权

US08732640B1 Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects 有权
标题翻译：用于多场景物理感知设计方法的方法，系统和文章，用于与布局相关的效果
公开(公告)号：US08732640B1
公开(公告)日：2014-05-20
申请号：US13282362
申请日：2011-10-26
申请人： Prakash Krishnan , Elias Fallon
发明人： Prakash Krishnan , Elias Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different layout contexts. The method may extract parasitics between components and analyzes impact(s) of layout dependent effect(s) on an electronic design by performing simulation(s) with layout dependent effect(s) in the schematic domain and may perform some partial routing based on some routing style(s) in each of the different layout contexts to generate just enough interconnects that may affect the electronic design.
摘要翻译：公开了用于实现电子电路设计的多场景物理感知设计的方法，系统和制品。在一些实施例中，当在物理设计中创建对应于多个候选配置的关键组件实例时，该方法捕获与布局相关的效果，以使得设计者能够从布局替换中创建部分布局，并从不同布局上下文中的部分布局中提取参数。该方法可以提取组件之间的寄生效应，并且通过在示意性域中执行具有布局相关效应的模拟来分析对电子设计的布局相关效应的影响，并且可以基于一些部分路由执行一些部分路由每个不同布局环境中的路由样式，以生成可能影响电子设计的足够的互连。

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