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1. 发明申请

US20080104548A1 Method and system for tuning a circuit 失效
标题翻译：调谐电路的方法和系统
公开(公告)号：US20080104548A1
公开(公告)日：2008-05-01
申请号：US11580735
申请日：2006-10-12
申请人： Rongchang Yan , Prakash Gopalakrishnan
发明人： Rongchang Yan , Prakash Gopalakrishnan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that meets a set of predefined design specifications, and the circuit comprises a group of circuit devices. The method further includes receiving a set of tuning information for the group of circuit devices tuning the group of circuit devices using the set of tuning information to create a group of tuned circuit devices, creating an updated layout of the group of tuned circuit devices using a layout tool, creating estimated parasitic information of the group of tuned circuit devices using the updated layout, and verifying the design point meets design goals of the circuit using the estimated parasitic information of the updated layout.
摘要翻译：本发明涉及一种用于调谐电路的方法和系统。在一个实施例中，该方法包括接收电路的描述，以及使用尺寸调整工具选择用于评估的电路的设计点，其中设计点包括满足一组预定设计规范的电路的设计，以及电路包括一组电路装置。该方法还包括接收用于使用该组调谐信息调谐该组电路装置的一组电路装置的一组调谐信息，以创建一组调谐电路装置，使用一个调谐电路装置创建该组调谐电路装置的更新布局使用更新的布局创建调谐电路器件组的估计寄生信息，并使用所估计的更新布局的寄生信息来验证设计点来满足电路的设计目标。

2. 发明授权

US08584072B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
标题翻译：在电路设计和使用不同精度模式的寄生感知电路设计中对布局进行建模的技术
公开(公告)号：US08584072B1
公开(公告)日：2013-11-12
申请号：US13601757
申请日：2012-08-31
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
摘要翻译：向用户呈现模拟环境，在该环境中用户被提供用于在不同精度的寄生模拟模式之间进行选择，模式包括不具有寄生效应的模式以及包括具有不同精度的寄生效应的多种模式。从用户接收到各种模式之间的选择，并以选定的准确度进行模拟测试。

3. 发明授权

US08261228B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
标题翻译：在电路设计和使用不同精度模式的寄生感知电路设计中对布局进行建模的技术
公开(公告)号：US08261228B1
公开(公告)日：2012-09-04
申请号：US12243394
申请日：2008-10-01
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment. In yet other techniques, a user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
摘要翻译：介绍了在集成电路自动化设计中考虑寄生效应的技术。在一组技术中，在用户的原理图环境中接收寄生模型的模型值，使用接收的模型值从原理图评估寄生模型，寄生模型被传送到布局环境，并且传递的寄生模型在布局环境中进行评估。在其他技术中，接收来自用户的寄生模型的模型值，在布局环境中对寄生模型进行评估，然后该过程将对布局环境评估的寄生模型和相应的参数值反馈到原理图环境。在其它技术中，向用户呈现模拟环境，在该模拟环境中，向用户提供选择以选择不同精度的寄生模拟模式，包括不具有寄生效应的模式，以及多种模式，包括具有不同程度的准确性。从用户接收到各种模式之间的选择，并以选定的准确度进行模拟测试。

4. 发明申请

US20120023465A1 METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS 有权
标题翻译：用于实现电子电路设计的制造方法，系统和制造与模拟意识
公开(公告)号：US20120023465A1
公开(公告)日：2012-01-26
申请号：US12982790
申请日：2010-12-30
申请人： Prakash GOPALAKRISHNAN , Michael MCSHERRY , David WHITE , Ed FISCHER , Bruce YANAGIDA , Keith DENNISON
发明人： Prakash GOPALAKRISHNAN , Michael MCSHERRY , David WHITE , Ed FISCHER , Bruce YANAGIDA , Keith DENNISON
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
摘要翻译：公开了实现具有模拟意识的电子设计的方法，系统和制造。在原理图级别识别或创建和模拟原理图，以表征电路的功能特性或确保电路设计符合要求的设计规范。识别，创建或更新设计组件的物理数据，并对与物理数据相关的电子寄存进行表征。与寄生相关联的一个或多个电特性被进一步表征并映射到仿真器以重新模拟电路设计以分析寄生效应的影响。一些实施例通过接受来自设计环境的增量设计或参数改变以交互方式递增地重新运行相同的模拟过程。

5. 发明授权

US08612921B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
公开(公告)号：US08612921B1
公开(公告)日：2013-12-17
申请号：US13601635
申请日：2012-08-31
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

6. 发明申请

US20120022846A1 METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS 有权
标题翻译：电子电路设计实现电动意识的方法，系统和制造文章
公开(公告)号：US20120022846A1
公开(公告)日：2012-01-26
申请号：US12982762
申请日：2010-12-30
申请人： David WHITE , Michael MCSHERRY , Ed FISCHER , Bruce YANAGIDA , Prakash GOPALAKRISHNAN
发明人： David WHITE , Michael MCSHERRY , Ed FISCHER , Bruce YANAGIDA , Prakash GOPALAKRISHNAN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.
摘要翻译：公开了用于实现具有电迁移意识的电子电路设计的方法，系统和制造。一些实施例执行示意性级仿真以确定电特性，识别布局组件的物理寄生效应，确定与组件上的电迁移分析相关联的电或物理特性，并且确定该组件是否满足EM相关约束同时在一些实施例中实现电子电路的物理设计。一些实施例进一步确定对于不符合EM相关约束的组件或相关数据的调整和/或以提示的形式呈现调整。各种数据和信息，例如各种形式或电压的电流，在各种示意图级别的工具和物理级别工具之间传递。

7. 发明授权

US07584440B2 Method and system for tuning a circuit 失效
标题翻译：调谐电路的方法和系统
公开(公告)号：US07584440B2
公开(公告)日：2009-09-01
申请号：US11580735
申请日：2006-10-12
申请人： Rongchang Yan , Prakash Gopalakrishnan
发明人： Rongchang Yan , Prakash Gopalakrishnan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that meets a set of predefined design specifications, and the circuit comprises a group of circuit devices. The method further includes receiving a set of tuning information for the group of circuit devices tuning the group of circuit devices using the set of tuning information to create a group of tuned circuit devices, creating an updated layout of the group of tuned circuit devices using a layout tool, creating estimated parasitic information of the group of tuned circuit devices using the updated layout, and verifying the design point meets design goals of the circuit using the estimated parasitic information of the updated layout.
摘要翻译：本发明涉及一种用于调谐电路的方法和系统。在一个实施例中，该方法包括接收电路的描述，以及使用尺寸调整工具选择用于评估的电路的设计点，其中设计点包括满足一组预定设计规范的电路的设计，以及电路包括一组电路装置。该方法还包括接收用于使用该组调谐信息调谐该组电路装置的一组电路装置的一组调谐信息，以创建一组调谐电路装置，使用一个调谐电路装置创建该组调谐电路装置的更新布局使用更新的布局创建调谐电路器件组的估计寄生信息，并使用所估计的更新布局的寄生信息验证设计点来满足电路的设计目标。

8. 发明授权

US07533358B2 Integrated sizing, layout, and extractor tool for circuit design 失效
标题翻译：用于电路设计的集成尺寸，布局和提取器工具
公开(公告)号：US07533358B2
公开(公告)日：2009-05-12
申请号：US11580637
申请日：2006-10-12
申请人： Prakash Gopalakrishnan , Hongzhou Liu
发明人： Prakash Gopalakrishnan , Hongzhou Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of design points, where a design point comprises a design of the circuit that meets a set of predefined design specifications, determining sizes for the circuit using a size optimization iteration process, and pausing the sizing optimization iteration process periodically for updating parasitic information of the circuit. The method further includes selecting a subset of design points from the set of design points, generating a layout of the circuit using devices sizes obtained from the set of design points, generating an extracted netlist using the layout, wherein the extracted netlist includes parasitic information of the circuit, and simulating the circuit using the extracted netlist to verify the set of predefined design specifications are met.
摘要翻译：公开了使用集成尺寸，布局和提取器工具设计电路的方法和系统。在一个实施例中，一种用于设计电路的方法，包括初始化一组设计点，其中设计点包括满足一组预定义设计规范的电路的设计，使用尺寸优化迭代过程确定电路的尺寸，以及周期性地暂停尺寸优化迭代处理，以更新电路的寄生信息。该方法还包括从该组设计点选择设计点的子集，使用从该组设计点获得的设备尺寸生成电路的布局，使用布局生成提取的网表，其中所提取的网表包括电路和使用提取的网表模拟电路以验证预定义的设计规范的集合。

9. 发明申请

US20080104557A1 Integrated sizing, layout, and extractor tool for circuit design 失效
标题翻译：用于电路设计的集成尺寸，布局和提取器工具
公开(公告)号：US20080104557A1
公开(公告)日：2008-05-01
申请号：US11580637
申请日：2006-10-12
申请人： Prakash Gopalakrishnan , Hongzhou Liu
发明人： Prakash Gopalakrishnan , Hongzhou Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of design points, where a design point comprises a design of the circuit that meets a set of predefined design specifications, determining sizes for the circuit using a size optimization iteration process, and pausing the sizing optimization iteration process periodically for updating parasitic information of the circuit. The method further includes selecting a subset of design points from the set of design points, generating a layout of the circuit using devices sizes obtained from the set of design points, generating an extracted netlist using the layout, wherein the extracted netlist includes parasitic information of the circuit, and simulating the circuit using the extracted netlist to verify the set of predefined design specifications are met.
摘要翻译：公开了使用集成尺寸，布局和提取器工具设计电路的方法和系统。在一个实施例中，一种用于设计电路的方法，包括初始化一组设计点，其中设计点包括满足一组预定义设计规范的电路的设计，使用尺寸优化迭代过程确定电路的尺寸，以及周期性地暂停尺寸优化迭代处理，以更新电路的寄生信息。该方法还包括从该组设计点选择设计点的子集，使用从该组设计点获得的设备尺寸生成电路的布局，使用布局生成提取的网表，其中所提取的网表包括电路和使用提取的网表模拟电路以验证预定义的设计规范的集合。

10. 发明授权

US06874133B2 Integrated circuit design layout compaction method 有权
标题翻译：集成电路设计布局压实方法
公开(公告)号：US06874133B2
公开(公告)日：2005-03-29
申请号：US10309958
申请日：2002-12-04
申请人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
发明人： Prakash Gopalakrishnan , Rob A. Rutenbar , Elias Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.
摘要翻译：多个构件装置被限定在具有一对间隔开的平行侧面的保形轮廓中。与每个成员设备相关联的是间距约束，其设定成员设备与另一个成员设备和保形轮廓的每一侧间隔的最小距离。根据需要增加和/或减小构件装置和/或共形轮廓的侧面之间的间隔，以使成员装置接收的保形轮廓的面积最小化，而不违反间隔约束，同时从保形轮廓排除其中定义的任何非成员设备的全部或部分。

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