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1. 发明授权

US06771545B1 Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权
标题翻译：用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法
公开(公告)号：US06771545B1
公开(公告)日：2004-08-03
申请号：US10353558
申请日：2003-01-29
申请人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
发明人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
IPC分类号： G11C1604
CPC分类号： G11C29/82 , G11C16/0491 , G11C16/3404
摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.
摘要翻译：非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。所选择的多个存储单元表示数据模式的一部分。识别非活动存储器单元编程模式。非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除，在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。在第一非活动列中的所选择的多个存储器单元上存储电荷。读取在第一活动列内的每个存储单元的数据模式。

2. 发明授权

US06788583B2 Pre-charge method for reading a non-volatile memory cell 失效
标题翻译：用于读取非易失性存储单元的预充电方法
公开(公告)号：US06788583B2
公开(公告)日：2004-09-07
申请号：US10307749
申请日：2002-12-02
申请人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
发明人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
摘要翻译：一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域线。将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

3. 发明授权

US06967873B2 Memory device and method using positive gate stress to recover overerased cell 有权
公开(公告)号：US06967873B2
公开(公告)日：2005-11-22
申请号：US10677790
申请日：2003-10-02
申请人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

4. 发明授权

US06897110B1 Method of protecting a memory array from charge damage during fabrication 有权
标题翻译：在制造期间保护存储器阵列免受电荷损伤的方法
公开(公告)号：US06897110B1
公开(公告)日：2005-05-24
申请号：US10305750
申请日：2002-11-26
申请人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
发明人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
IPC分类号： H01L21/336 , H01L21/4763 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.
摘要翻译：一种制造存储器阵列的方法，同时保护其免受电荷损坏。可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。字线形成在位线之上，并且可以具有栅极区域。接下来，在位线之上形成耦合到位线之一的第一金属区域。形成不与第一金属区电耦合的第二金属区域。然后，第一金属区域电耦合到第二金属区域。通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。此外，可以在位线和字线之间形成保险丝，以保护字线。

5. 发明授权

US06956768B2 Method of programming dual cell memory device to store multiple data states per cell 有权
标题翻译：编程双单元存储器件以存储每个单元的多个数据状态的方法
公开(公告)号：US06956768B2
公开(公告)日：2005-10-18
申请号：US10413800
申请日：2003-04-15
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10
摘要： A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.
摘要翻译：一种编程多级双电池存储器件的方法。该方法包括将第一电荷存储单元和第二电荷存储单元独立地编程为相应的数据状态，从空白程序级或多个带电程序级中的一个选择的数据状态。还公开了一种使用多个参考电流读取多电平双电池存储器件的方法。

6. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

7. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

8. 发明申请

US20050153508A1 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
公开(公告)号：US20050153508A1
公开(公告)日：2005-07-14
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
发明人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

9. 发明授权

US07995386B2 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb 有权
标题翻译：将负栅极电压施加到与读取或验证相关的字线附近的字线，以减少相邻的字线干扰
公开(公告)号：US07995386B2
公开(公告)日：2011-08-09
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译：提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

10. 发明授权

US06795357B1 Method for reading a non-volatile memory cell 失效
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US06795357B1
公开(公告)日：2004-09-21
申请号：US10283590
申请日：2002-10-30
申请人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
发明人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C700
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/26
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.
摘要翻译：检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加到与沟道区形成漏极结的第二位线的漏极电压。源极电压可以是小的正电压，并且漏极电压可能大于源极电压。将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。偏置电压可以是负电压。

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