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1. 发明申请

US20080037330A1 RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY 有权
标题翻译：用于双位闪存存储器的RAMP GATE擦除
公开(公告)号：US20080037330A1
公开(公告)日：2008-02-14
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

2. 发明申请

US20080151644A1 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US20080151644A1
公开(公告)日：2008-06-26
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

3. 发明授权

US06834012B1 Memory device and methods of using negative gate stress to correct over-erased memory cells 有权
标题翻译：存储器件和使用负栅极应力校正过擦除存储器单元的方法
公开(公告)号：US06834012B1
公开(公告)日：2004-12-21
申请号：US10863673
申请日：2004-06-08
申请人： Yi He , Edward Franklin Runnion , Zhizheng Liu , Zengtao Liu , Mark William Randolph
发明人： Yi He , Edward Franklin Runnion , Zhizheng Liu , Zengtao Liu , Mark William Randolph
IPC分类号： G11C1604
CPC分类号： G11C16/3404 , G11C16/0475
摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.
摘要翻译：提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。

4. 发明申请

US20090154251A1 ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT 有权
标题翻译：减少电荷损失和分配改进的算法
公开(公告)号：US20090154251A1
公开(公告)日：2009-06-18
申请号：US11959122
申请日：2007-12-18
申请人： Gwyn Robert Jones , Edward Franklin Runnion , Zhizheng Liu , Mark William Randolph
发明人： Gwyn Robert Jones , Edward Franklin Runnion , Zhizheng Liu , Mark William Randolph
IPC分类号： G11C7/00
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C2211/5621
摘要： Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.
摘要翻译：提供了用于在存储器件的选定字线上精确编程或擦除一个或多个存储器单元的方法和系统。在一个实施例中，存储器件包括存储器阵列，阈值电压测量部件，被配置为测量存储器阵列的选定字线上的每个存储器单元的阈值电压，以及平均阈值电压确定部件，被配置为确定平均阈值电压结果与所选择的字线唯一地相关联，基于所测量的阈值电压。存储器装置被配置为相对于所确定的平均阈值电压将一个或多个存储器单元编程到预定程序级，或者将所选字线的存储单元擦除到所确定的平均阈值电压。该方法对于多级闪存单元特别有用，以减少电荷损耗，同时提高编程元件状态的数据可靠性和Vt分布。

5. 发明申请

US20100128521A1 APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB 有权
标题翻译：应用负极门电压到相关的字词相关联的阅读或验证，以减少相似词干扰
公开(公告)号：US20100128521A1
公开(公告)日：2010-05-27
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译：提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

6. 发明授权

US07619932B2 Algorithm for charge loss reduction and Vt distribution improvement 有权
标题翻译：电荷损失减少和Vt分布改进的算法
公开(公告)号：US07619932B2
公开(公告)日：2009-11-17
申请号：US11959122
申请日：2007-12-18
申请人： Gwyn Robert Jones , Edward Franklin Runnion , Zhizheng Liu , Mark William Randolph
发明人： Gwyn Robert Jones , Edward Franklin Runnion , Zhizheng Liu , Mark William Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C2211/5621
摘要： Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.
摘要翻译：提供了用于在存储器件的选定字线上精确编程或擦除一个或多个存储器单元的方法和系统。在一个实施例中，存储器件包括存储器阵列，阈值电压测量部件，被配置为测量存储器阵列的选定字线上的每个存储器单元的阈值电压，以及平均阈值电压确定部件，被配置为确定平均阈值电压结果与所选择的字线唯一地相关联，基于所测量的阈值电压。存储器装置被配置为相对于所确定的平均阈值电压将一个或多个存储器单元编程到预定程序级，或者将所选字线的存储单元擦除到所确定的平均阈值电压。该方法对于多级闪存单元特别有用，以减少电荷损耗，同时提高编程元件状态的数据可靠性和Vt分布。

7. 发明授权

US07995386B2 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb 有权
标题翻译：将负栅极电压施加到与读取或验证相关的字线附近的字线，以减少相邻的字线干扰
公开(公告)号：US07995386B2
公开(公告)日：2011-08-09
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译：提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

8. 发明授权

US07561471B2 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US07561471B2
公开(公告)日：2009-07-14
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

9. 发明授权

US07319615B1 Ramp gate erase for dual bit flash memory 有权
标题翻译：用于双位闪存的斜坡栅极擦除
公开(公告)号：US07319615B1
公开(公告)日：2008-01-15
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

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