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1. 发明授权

US4985640A Apparatus for generating computer clock pulses 失效
标题翻译：用于产生计算机时钟脉冲的装置
公开(公告)号：US4985640A
公开(公告)日：1991-01-15
申请号：US472598
申请日：1990-04-04
申请人： Edward Grochowski , Rajesh Gupta
发明人： Edward Grochowski , Rajesh Gupta
IPC分类号： H03K5/15 , H03K5/151
CPC分类号： H03K5/151 , H03K5/15006
摘要： A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases; apparatus for producing a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator; and apparatus responsive to the apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases for equalizing the duty cycle of the pair of closk pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator.
摘要翻译：一种用于产生相对相位的一对时钟脉冲的电路，每个时钟脉冲具有与由晶体振荡器产生的输入信号的频率相同的频率，该晶体振荡器包括用于产生第一和第二对信号的信号，所述第一和第二对信号的频率为由晶体振荡器，每对信号彼此相反; 用于将第一对信号的第一信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 用于将第一对信号的第二信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 利用所述输出信号之一来延长所述第一对相对相位信号中的一个的占空比以及所述输出信号中的另一个的占空比，以缩短所述第一对相对相位信号中另一个的占空比; 用于产生具有与由晶体振荡器产生的输入信号的频率相同频率的相反相位的一对时钟脉冲的装置; 以及响应于所述装置的设备，利用所述输出信号之一来延长所述第一对相对相位信号之一的占空比，并且输出信号中的另一个信号的占空比，以缩短所述第一对信号中另一个的相反的占空比用于均衡相位相对的一对闭合脉冲的占空比的相位，每个相位相位的频率与由晶体振荡器产生的输入信号的频率相同。

2. 发明申请

US20070164787A1 Method and apparatus for late timing transition detection 有权
标题翻译：用于后期定时转换检测的方法和装置
公开(公告)号：US20070164787A1
公开(公告)日：2007-07-19
申请号：US11234548
申请日：2005-09-23
申请人： Edward Grochowski , Chris Wilkerson , Shih-Lien Lu , Murali Annavaram
发明人： Edward Grochowski , Chris Wilkerson , Shih-Lien Lu , Murali Annavaram
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译：两个锁存器在时钟信号的转变时存储数据信号的状态。比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。描述和要求保护使用锁存器和比较逻辑的系统。

3. 发明授权

US06938126B2 Cache-line reuse-buffer 失效
标题翻译：缓存行重用缓冲区
公开(公告)号：US06938126B2
公开(公告)日：2005-08-30
申请号：US10121524
申请日：2002-04-12
申请人： Alejandro Ramirez , Edward Grochowski , Hong Wang , John Shen
发明人： Alejandro Ramirez , Edward Grochowski , Hong Wang , John Shen
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0882 , G06F12/0886 , Y02D10/13
摘要： A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.
摘要翻译：将具有第一起始地址和与当前取出请求相关联的长度的当前提取请求与下一个提取请求的第二起始地址进行比较的方法，装置和系统确定已经加载在缓冲器中的内容是否将被用于至少部分地基于比较来完成下一个提取请求，并且基于比较来禁止对指令高速缓存的访问。

4. 发明授权

US06904502B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06904502B2
公开(公告)日：2005-06-07
申请号：US10743069
申请日：2003-12-23
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F12/08 , G06F12/10 , G06F12/16 , G11C7/24
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.
摘要翻译：本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右，相邻的存储器位电路为零。

5. 发明授权

US06813628B2 Method and apparatus for performing equality comparison in redundant form arithmetic 有权
标题翻译：用于在冗余形式算术中执行等式比较的方法和装置
公开(公告)号：US06813628B2
公开(公告)日：2004-11-02
申请号：US09746771
申请日：2000-12-22
申请人： Bharat Bhushan , Edward Grochowski , Vinod Sharma , John Crawford
发明人： Bharat Bhushan , Edward Grochowski , Vinod Sharma , John Crawford
IPC分类号： G06F704
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/026 , G06F7/48 , G06F7/4824
摘要： A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.
摘要翻译：公开了一种方法和装置，用于比较相等的数字。减去以冗余形式表示的数字，包括从旁路电路接收的数字。更具体地，产生补码形式并将其提供给用冗余形式表示的至少一个数字的运算电路。调整运算电路的输入以增加通过算术电路产生的结果，以产生作为减法运算的结果以冗余形式表示的有效结果。使用非传播电路将减法操作的结果与冗余形式进行比较，而不需要进位传播，从而产生冗余形式的数量的等式比较。

6. 发明授权

US06775746B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
公开(公告)号：US06775746B2
公开(公告)日：2004-08-10
申请号：US10435386
申请日：2003-05-12
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F1210
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

7. 发明授权

US08125246B2 Method and apparatus for late timing transition detection 有权
标题翻译：用于后期定时转换检测的方法和装置
公开(公告)号：US08125246B2
公开(公告)日：2012-02-28
申请号：US12618629
申请日：2009-11-13
申请人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
发明人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
IPC分类号： H03K19/096
CPC分类号： G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译：两个锁存器在时钟信号的转变时存储数据信号的状态。比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。描述和要求保护使用锁存器和比较逻辑的系统。

8. 发明申请

US20100052730A1 METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION 有权
标题翻译：用于时间过渡检测的方法和装置
公开(公告)号：US20100052730A1
公开(公告)日：2010-03-04
申请号：US12618629
申请日：2009-11-13
申请人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
发明人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
IPC分类号： H03K5/19
CPC分类号： G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译：两个锁存器在时钟信号的转变时存储数据信号的状态。比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。描述和要求保护使用锁存器和比较逻辑的系统。

9. 发明授权

US07480838B1 Method, system and apparatus for detecting and recovering from timing errors 有权
标题翻译：从定时误差检测和恢复的方法，系统和装置
公开(公告)号：US07480838B1
公开(公告)日：2009-01-20
申请号：US11388668
申请日：2006-03-23
申请人： Chris Wilkerson , Shih-Lien L. Lu , Edward Grochowski , Murali Annavaram
发明人： Chris Wilkerson , Shih-Lien L. Lu , Edward Grochowski , Murali Annavaram
IPC分类号： G06K5/04
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0772 , G06F11/1497
摘要： Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.
摘要翻译：包括用于报告从电路电平到功能单元块（FUB）到全局检测的定时误差检测的层次结构的集成设备的检测内部定时误差的有效电路的方法和系统以及重新排序缓冲器（ROB），用于存储用于定时错误恢复的结果，直到定时可被验证为无错误。

10. 发明申请

US20050188185A1 Method and apparatus for predicate implementation using selective conversion to micro-operations 审中-公开
标题翻译：使用选择性转换为微操作进行谓词实现的方法和装置
公开(公告)号：US20050188185A1
公开(公告)日：2005-08-25
申请号：US10783765
申请日：2004-02-20
申请人： Edward Grochowski
发明人： Edward Grochowski
IPC分类号： G06F9/00 , G06F9/318
CPC分类号： G06F9/30072 , G06F9/30145
摘要： A method and apparatus for implementing predicated instructions using selective conversion to micro-operations is presented. In one embodiment, the predicated instructions may have both a prediction of the predicate value and an indication of the confidence value of that predicted predicate value generated. When the confidence value of the prediction is low, then the predicated instruction may be decomposed into a set of micro-operations that should execute whether the predicate value is true or false. But when the confidence value is high, then the predicated instruction may be decomposed into simpler sets of micro-operations, for the cases when the predicted predicate value is true and for when it is false.
摘要翻译：提出了一种使用选择性转换为微操作来实现预测指令的方法和装置。在一个实施例中，所述预测指令可以具有所述谓词值的预测和所生成的所述预测谓词值的置信度值的指示。当预测的置信度值低时，则可以将预测指令分解为应该执行谓词值是真还是假的一组微操作。但是，当置信度值高时，对于预测的谓词值为真，以及当为假时，预测指令可能被分解成更简单的微操作集合。

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