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1. 发明授权

US06839814B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06839814B2
公开(公告)日：2005-01-04
申请号：US10726492
申请日：2003-12-04
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.
摘要翻译：本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

2. 发明授权

US06675266B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06675266B2
公开(公告)日：2004-01-06
申请号：US09750094
申请日：2000-12-29
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F1200
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.
摘要翻译：本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。这些保护方案保护缓存中标签阵列中使用的1-hot向量，并且被设计为提供硬件节省，以更高的速度运行并且易于实现。根据本发明的实施例，标签阵列存储电路包括耦合在一起以形成n位存储单元的多个存储器位电路和耦合到n位存储单元的有效位电路，有效位电路被配置为与多个存储器位电路同时访问。

3. 发明授权

US07315920B2 Circuit and method for protecting vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的矢量标签的电路和方法
公开(公告)号：US07315920B2
公开(公告)日：2008-01-01
申请号：US11028293
申请日：2005-01-04
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F12/00
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.
摘要翻译：本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

4. 发明授权

US06904502B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06904502B2
公开(公告)日：2005-06-07
申请号：US10743069
申请日：2003-12-23
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F12/08 , G06F12/10 , G06F12/16 , G11C7/24
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.
摘要翻译：本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右，相邻的存储器位电路为零。

5. 发明授权

US06775746B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
公开(公告)号：US06775746B2
公开(公告)日：2004-08-10
申请号：US10435386
申请日：2003-05-12
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F1210
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

6. 发明授权

US06728800B1 Efficient performance based scheduling mechanism for handling multiple TLB operations 有权
标题翻译：用于处理多个TLB操作的基于性能的调度机制
公开(公告)号：US06728800B1
公开(公告)日：2004-04-27
申请号：US09606844
申请日：2000-06-28
申请人： Allisa Chiao-Er Lee , Greg S. Mathews
发明人： Allisa Chiao-Er Lee , Greg S. Mathews
IPC分类号： G06F1314
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and apparatus for an efficient performance based scheduling mechanism for handling multiple TLB operations. One method of the present invention comprises prioritizing a first translation lookaside buffer request and a second translation lookaside buffer request for handling. The first request is of a first type and the second request is of a second type. The first type having a higher priority than said second type.
摘要翻译：一种用于处理多个TLB操作的用于基于性能的调度机制的方法和装置。本发明的一种方法包括对第一翻译后备缓冲器请求和用于处理的第二翻译后备缓冲器请求进行优先级排序。第一个请求是第一个请求，第二个请求是第二个请求。第一类型具有比所述第二类型更高的优先级。

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