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1. 发明申请

US20120256653A1 PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES 失效
标题翻译：可编程逻辑电路采用三维堆叠技术
公开(公告)号：US20120256653A1
公开(公告)日：2012-10-11
申请号：US13080994
申请日：2011-04-06
申请人： Edgar R. Cordero , Robert B. Tremaine
发明人： Edgar R. Cordero , Robert B. Tremaine
IPC分类号： H03K19/003 , H03K19/177
CPC分类号： H03K19/08 , G11C29/08 , H03K19/17752 , H03K19/17796
摘要： A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.
摘要翻译：一种可配置的管芯堆叠装置，其包括位于第一衬底上的第一可配置集成电路管芯。第一可配置集成电路管芯包括第一阵列和第一配置存储器管理电路，其包括与第一阵列的接口。第一阵列包括第一逻辑元件和第一配置存储器。可配置管芯堆叠装置还包括位于与第一衬底不同的第二衬底上的第二可配置集成电路管芯。第二可配置集成电路管芯包括第二阵列和第二配置存储器管理电路，其包括到第二阵列的接口。第二阵列包括第二逻辑元件和第二配置存储器。信号耦合到第一配置管理电路和第二配置管理电路，并且第一配置存储器管理电路包括用于控制信号的电路。

2. 发明授权

US08493089B2 Programmable logic circuit using three-dimensional stacking techniques 失效
标题翻译：可编程逻辑电路采用三维堆叠技术
公开(公告)号：US08493089B2
公开(公告)日：2013-07-23
申请号：US13080994
申请日：2011-04-06
申请人： Edgar R. Cordero , Robert B. Tremaine
发明人： Edgar R. Cordero , Robert B. Tremaine
IPC分类号： H01L25/00
CPC分类号： H03K19/08 , G11C29/08 , H03K19/17752 , H03K19/17796
摘要： A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.
摘要翻译：一种可配置的管芯堆叠装置，其包括位于第一衬底上的第一可配置集成电路管芯。第一可配置集成电路管芯包括第一阵列和第一配置存储器管理电路，其包括与第一阵列的接口。第一阵列包括第一逻辑元件和第一配置存储器。可配置管芯堆叠装置还包括位于与第一衬底不同的第二衬底上的第二可配置集成电路管芯。第二可配置集成电路管芯包括第二阵列和第二配置存储器管理电路，其包括到第二阵列的接口。第二阵列包括第二逻辑元件和第二配置存储器。信号耦合到第一配置管理电路和第二配置管理电路，并且第一配置存储器管理电路包括用于控制信号的电路。

3. 发明授权

US09086957B2 Requesting a memory space by a memory controller 有权
标题翻译：通过内存控制器请求内存空间
公开(公告)号：US09086957B2
公开(公告)日：2015-07-21
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F3/06 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

4. 发明授权

US08692561B2 Implementing chip to chip calibration within a TSV stack 有权
标题翻译：在TSV堆栈内实现芯片到芯片校准
公开(公告)号：US08692561B2
公开(公告)日：2014-04-08
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： G01R35/00
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

5. 发明申请

US20140040576A1 REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER 有权
标题翻译：由记忆控制器请求记忆空间
公开(公告)号：US20140040576A1
公开(公告)日：2014-02-06
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

6. 发明申请

US20130038380A1 IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK 有权
标题翻译：在TSV堆栈中进行芯片校准
公开(公告)号：US20130038380A1
公开(公告)日：2013-02-14
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： H03H11/00 , G06F17/50 , H01L29/68
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

7. 发明授权

US08806177B2 Prefetch engine based translation prefetching 有权
标题翻译：预取引擎基于翻译预取
公开(公告)号：US08806177B2
公开(公告)日：2014-08-12
申请号：US11482222
申请日：2006-07-07
申请人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译：提供了一种在计算机系统中预取的方法和系统。该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。在预取期间解决翻译错误的处理和解决。该方法还包括将分辨的翻译存储在相应的缓存转换表中。用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。

8. 发明授权

US08674856B2 Data compression utilizing longest common subsequence template 失效
标题翻译：使用最长公共子序列模板的数据压缩
公开(公告)号：US08674856B2
公开(公告)日：2014-03-18
申请号：US13587669
申请日：2012-08-16
申请人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
发明人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
IPC分类号： H03M7/34
CPC分类号： H03M7/30 , H03M7/607
摘要： In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.
摘要翻译：响应于输入字符串的接收，尝试在模板存储器中识别紧密匹配的模板以用作压缩模板。响应于可以用作压缩模板的紧密匹配的模板的识别，通过参考最长的公共子序列压缩模板将输入字符串压缩成压缩字符串。压缩输入字符串包括在压缩字符串中编码压缩模板的标识符，将与压缩模板具有至少预定长度的压缩模板不一致的输入字符串的子串编码为文字，以及编码具有共同性的输入字符串的子串至少具有预定长度的压缩模板作为跳跃距离，而不参考压缩模板中的基本位置。然后输出压缩字符串。

9. 发明授权

US08513972B2 Soft error resilient FPGA 失效
公开(公告)号：US08513972B2
公开(公告)日：2013-08-20
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

10. 发明申请

US20120023300A1 MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM 有权
标题翻译：一个层次化的记忆系统中的存储页面管理
公开(公告)号：US20120023300A1
公开(公告)日：2012-01-26
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F12/14
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

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