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1. 发明授权

US08692561B2 Implementing chip to chip calibration within a TSV stack 有权
标题翻译：在TSV堆栈内实现芯片到芯片校准
公开(公告)号：US08692561B2
公开(公告)日：2014-04-08
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： G01R35/00
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

2. 发明申请

US20130038380A1 IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK 有权
标题翻译：在TSV堆栈中进行芯片校准
公开(公告)号：US20130038380A1
公开(公告)日：2013-02-14
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： H03H11/00 , G06F17/50 , H01L29/68
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

3. 发明授权

US08930776B2 Implementing DRAM command timing adjustments to alleviate DRAM failures 有权
标题翻译：实施DRAM命令定时调整以减轻DRAM故障
公开(公告)号：US08930776B2
公开(公告)日：2015-01-06
申请号：US13598072
申请日：2012-08-29
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/00
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译：提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。检测到预定义的DRAM故障。响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。

4. 发明申请

US20130179724A1 IIMPLEMENTING ENHANCED HARDWARE ASSISTED DRAM REPAIR 有权
标题翻译：增强硬件辅助的DRAM修复
公开(公告)号：US20130179724A1
公开(公告)日：2013-07-11
申请号：US13343938
申请日：2012-01-05
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/20
CPC分类号： G06F11/1666 , G06F11/1048 , G06F11/141 , G06F11/20 , G11C29/76
摘要： A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.
摘要翻译：提供了一种在支持ECC的计算机系统中实现硬件辅助动态随机存取存储器（DRAM）修复的方法，系统和计算机程序产品。提供DRAM修复的数据寄存器被选择性地提供在动态随机存取存储器（DRAM），存储器控制器或耦合在DRAM和存储器控制器之间的存储缓冲器之一中。数据寄存器被配置为映射到任何地址。响应于所检测到的配置地址，从配置的地址的读取或写入路由到数据寄存器。

5. 发明授权

US09063902B2 Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module 有权
标题翻译：在DRAM模块中选择性地提供使用用于DRAM修复的数据寄存器来实现增强的硬件辅助DRAM修复
公开(公告)号：US09063902B2
公开(公告)日：2015-06-23
申请号：US13343938
申请日：2012-01-05
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/18 , G06F11/16 , G11C29/00 , G06F11/10 , G06F11/20 , G06F11/14
CPC分类号： G06F11/1666 , G06F11/1048 , G06F11/141 , G06F11/20 , G11C29/76
摘要： A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.
摘要翻译：提供了一种在支持ECC的计算机系统中实现硬件辅助动态随机存取存储器（DRAM）修复的方法，系统和计算机程序产品。提供DRAM修复的数据寄存器被选择性地提供在动态随机存取存储器（DRAM），存储器控制器或耦合在DRAM和存储器控制器之间的存储缓冲器之一中。数据寄存器被配置为映射到任何地址。响应于所检测到的配置地址，从配置的地址的读取或写入路由到数据寄存器。

6. 发明申请

US20140068322A1 IIMPLEMENTING DRAM COMMAND TIMING ADJUSTMENTS TO ALLEVIATE DRAM FAILURES 有权
标题翻译：将DRAM命令定时调整到可靠的DRAM故障
公开(公告)号：US20140068322A1
公开(公告)日：2014-03-06
申请号：US13598072
申请日：2012-08-29
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/14
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译：提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。检测到预定义的DRAM故障。响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。

7. 发明申请

US20120256653A1 PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES 失效
标题翻译：可编程逻辑电路采用三维堆叠技术
公开(公告)号：US20120256653A1
公开(公告)日：2012-10-11
申请号：US13080994
申请日：2011-04-06
申请人： Edgar R. Cordero , Robert B. Tremaine
发明人： Edgar R. Cordero , Robert B. Tremaine
IPC分类号： H03K19/003 , H03K19/177
CPC分类号： H03K19/08 , G11C29/08 , H03K19/17752 , H03K19/17796
摘要： A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.
摘要翻译：一种可配置的管芯堆叠装置，其包括位于第一衬底上的第一可配置集成电路管芯。第一可配置集成电路管芯包括第一阵列和第一配置存储器管理电路，其包括与第一阵列的接口。第一阵列包括第一逻辑元件和第一配置存储器。可配置管芯堆叠装置还包括位于与第一衬底不同的第二衬底上的第二可配置集成电路管芯。第二可配置集成电路管芯包括第二阵列和第二配置存储器管理电路，其包括到第二阵列的接口。第二阵列包括第二逻辑元件和第二配置存储器。信号耦合到第一配置管理电路和第二配置管理电路，并且第一配置存储器管理电路包括用于控制信号的电路。

8. 发明授权

US08493089B2 Programmable logic circuit using three-dimensional stacking techniques 失效
标题翻译：可编程逻辑电路采用三维堆叠技术
公开(公告)号：US08493089B2
公开(公告)日：2013-07-23
申请号：US13080994
申请日：2011-04-06
申请人： Edgar R. Cordero , Robert B. Tremaine
发明人： Edgar R. Cordero , Robert B. Tremaine
IPC分类号： H01L25/00
CPC分类号： H03K19/08 , G11C29/08 , H03K19/17752 , H03K19/17796
摘要： A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.
摘要翻译：一种可配置的管芯堆叠装置，其包括位于第一衬底上的第一可配置集成电路管芯。第一可配置集成电路管芯包括第一阵列和第一配置存储器管理电路，其包括与第一阵列的接口。第一阵列包括第一逻辑元件和第一配置存储器。可配置管芯堆叠装置还包括位于与第一衬底不同的第二衬底上的第二可配置集成电路管芯。第二可配置集成电路管芯包括第二阵列和第二配置存储器管理电路，其包括到第二阵列的接口。第二阵列包括第二逻辑元件和第二配置存储器。信号耦合到第一配置管理电路和第二配置管理电路，并且第一配置存储器管理电路包括用于控制信号的电路。

9. 发明授权

US09086957B2 Requesting a memory space by a memory controller 有权
标题翻译：通过内存控制器请求内存空间
公开(公告)号：US09086957B2
公开(公告)日：2015-07-21
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F3/06 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

10. 发明申请

US20140040576A1 REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER 有权
标题翻译：由记忆控制器请求记忆空间
公开(公告)号：US20140040576A1
公开(公告)日：2014-02-06
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

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