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1. 发明申请

US20060047934A1 Integrated circuit capable of memory access control 审中-公开
标题翻译：具有内存访问控制的集成电路
公开(公告)号：US20060047934A1
公开(公告)日：2006-03-02
申请号：US10931278
申请日：2004-08-31
申请人： Mark Schmisseur , Joseph Murray , Richard Mackey , Micheil Lee
发明人： Mark Schmisseur , Joseph Murray , Richard Mackey , Micheil Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/12
摘要： A method according to one embodiment may include selecting a port, among a plurality of ports. The method of this embodiment may also include selecting between a memory read request and a memory write request from at least one port, among the plurality of ports, based on, at least in part, at least one memory access rule. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括在多个端口之中选择端口。该实施例的方法还可以包括至少部分地基于至少一个存储器访问规则来选择在多个端口中的至少一个端口的存储器读请求和存储器写请求之间。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明申请

US20060168359A1 METHOD, SYSTEM, AND PROGRAM FOR HANDLING INPUT/OUTPUT COMMANDS 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US20060168359A1
公开(公告)日：2006-07-27
申请号：US11279086
申请日：2006-04-07
申请人： Sailesh Bissessur , Richard Mackey , Mark Schmisseur , David Smith
发明人： Sailesh Bissessur , Richard Mackey , Mark Schmisseur , David Smith
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。设备控制器被允许从总线上的启动器向预定义的地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

3. 发明申请

US20070112665A1 Method and system for electronic trading via a yield curve 有权
标题翻译：通过收益曲线进行电子交易的方法和系统
公开(公告)号：US20070112665A1
公开(公告)日：2007-05-17
申请号：US11595498
申请日：2006-11-10
申请人： Richard Mackey , Edward Harvey
发明人： Richard Mackey , Edward Harvey
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q40/02
摘要： A method and system for providing electronic trading via yield curves. The method and system allow automatic execution of electronic trades with yield curve trading strategies using real, synthetic, black box, spread, and supply differential yield curve trading information.
摘要翻译：一种通过收益曲线提供电子交易的方法和系统。该方法和系统允许使用实际，合成，黑盒，差价和供应差异收益率曲线交易信息自动执行电子交易与收益曲线交易策略。

4. 发明申请

US20060212639A1 Bus segment decoder 有权
标题翻译：总线段解码器
公开(公告)号：US20060212639A1
公开(公告)日：2006-09-21
申请号：US11418600
申请日：2006-05-05
申请人： Richard Mackey
发明人： Richard Mackey
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus environment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.
摘要翻译：公开了一种在多个数据总线环境中将总线事务从源设备转发到目标设备的系统和方法。当目标设备在数据总线地址处耦合到第一数据总线时，桥耦合在第一数据总线和第二数据总线之间。解码器可以独立于由源设备发起的第二数据总线上的总线事务向桥提供总线段信息。桥可以包括基于总线段信息将第一数据总线上的总线事务转发到目标设备的逻辑。

5. 发明申请

US20060294447A1 Apparatus and method for parity generation in a data-packing device 失效
公开(公告)号：US20060294447A1
公开(公告)日：2006-12-28
申请号：US11171086
申请日：2005-06-27
申请人： Richard Mackey
发明人： Richard Mackey
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G06F11/108
摘要： A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.

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