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1. 发明授权

US06787838B1 Trench capacitor DRAM cell using buried oxide as array top oxide 有权
标题翻译：沟槽电容器DRAM单元采用埋置氧化物作为阵列顶部氧化物
公开(公告)号：US06787838B1
公开(公告)日：2004-09-07
申请号：US10250259
申请日：2003-06-18
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/1203
摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与基质。

2. 发明授权

US07195972B2 Trench capacitor DRAM cell using buried oxide as array top oxide 失效
标题翻译：沟槽电容器DRAM单元采用埋置氧化物作为阵列顶部氧化物
公开(公告)号：US07195972B2
公开(公告)日：2007-03-27
申请号：US10886439
申请日：2004-07-06
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/1203
摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与基质。

3. 发明申请

US20050064710A1 Trench capacitor DRAM cell using buried oxide as array top oxide 失效
标题翻译：沟槽电容器DRAM单元采用埋置氧化物作为阵列顶部氧化物
公开(公告)号：US20050064710A1
公开(公告)日：2005-03-24
申请号：US10886439
申请日：2004-07-06
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
IPC分类号： H01L27/108 , H01L21/20 , H01L21/302 , H01L21/461 , H01L21/8242 , H01L27/12
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/1203
摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与基质。

4. 发明申请

US20060091442A1 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US20060091442A1
公开(公告)日：2006-05-04
申请号：US11298800
申请日：2005-12-09
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

5. 发明授权

US06777737B2 Vertical DRAM punchthrough stop self-aligned to storage trench 有权
标题翻译：垂直DRAM穿透停止自对准到存储沟槽
公开(公告)号：US06777737B2
公开(公告)日：2004-08-17
申请号：US10016605
申请日：2001-10-30
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要翻译：具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。每个存储单元包括覆盖沟槽电容器的垂直晶体管。在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。

6. 发明申请

US20080261128A1 Methods and structures for protecting one area while processing another area on a chip 有权
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US20080261128A1
公开(公告)日：2008-10-23
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03F7/004 , G03F7/20
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

7. 发明申请

US20050255386A1 METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP 失效
标题翻译：在芯片上处理其他区域时保护一个区域的方法和结构
公开(公告)号：US20050255386A1
公开(公告)日：2005-11-17
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03C5/00 , G03F7/11 , G03F9/00 , H01L21/033 , H01L21/311 , H01L21/331
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

8. 发明授权

US07601646B2 Top-oxide-early process and array top oxide planarization 有权
标题翻译：顶部氧化物早期过程和阵列顶部氧化物平面化
公开(公告)号：US07601646B2
公开(公告)日：2009-10-13
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

9. 发明申请

US20060226481A1 SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION: METHOD AND STRUCTURE 有权
标题翻译：简化的垂直阵列设备DRAM / eDRAM集成：方法和结构
公开(公告)号：US20060226481A1
公开(公告)日：2006-10-12
申请号：US10907630
申请日：2005-04-08
申请人： Deok-kee Kim , Ramachandra Divakaruni , Carl Radens , Dae-Gyu Park
发明人： Deok-kee Kim , Ramachandra Divakaruni , Carl Radens , Dae-Gyu Park
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , H01L27/10841 , H01L27/10891
摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
摘要翻译：本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。根据本发明，被动字线通过衬垫氮化物与有源区分离。本发明还提供了能够形成本发明的半导体结构的方法。

10. 发明申请

US20060019443A1 TOP-OXIDE-EARLY PROCESS AND ARRAY TOP OXIDE PLANARIZATION 有权
标题翻译：前氧化物早期工艺和顶部氧化物平面排列
公开(公告)号：US20060019443A1
公开(公告)日：2006-01-26
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/467 , H01L21/8242
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

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