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1. 发明授权

US07601646B2 Top-oxide-early process and array top oxide planarization 有权
标题翻译：顶部氧化物早期过程和阵列顶部氧化物平面化
公开(公告)号：US07601646B2
公开(公告)日：2009-10-13
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

2. 发明申请

US20060019443A1 TOP-OXIDE-EARLY PROCESS AND ARRAY TOP OXIDE PLANARIZATION 有权
标题翻译：前氧化物早期工艺和顶部氧化物平面排列
公开(公告)号：US20060019443A1
公开(公告)日：2006-01-26
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/467 , H01L21/8242
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

3. 发明申请

US20050260859A1 METHOD FOR PATTERNING A SEMICONDUCTOR REGION 失效
标题翻译：用于绘制半导体区域的方法
公开(公告)号：US20050260859A1
公开(公告)日：2005-11-24
申请号：US10709673
申请日：2004-05-21
申请人： Sadanand Deshpande , Rajiv Ranade , George Worth
发明人： Sadanand Deshpande , Rajiv Ranade , George Worth
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/461 , H01L29/49
CPC分类号： H01L21/28035 , H01L21/32137 , H01L29/4925
摘要： A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.
摘要翻译：提供了可以重掺杂的半导体区域图形化的方法。在半导体区域上方设置图案化掩模。通过图案化掩模曝光的半导体区域的一部分在包括聚合碳氟化合物，例如碳与氟原子比高的无氯碳氟化合物的环境中被蚀刻，以及至少一种选自下组的非聚合物质由非聚合碳氟化合物组成，例如碳与氟原子比低的氢化碳氟化合物。该方法优选地钝化图案化的半导体区域的侧壁，使得可以在图案化区域下方的半导体材料的下部区域被定向蚀刻，而不会侵蚀如此钝化的图案化区域。

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