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1. 发明授权

US07949863B2 Inter-port communication in a multi-port memory device 有权
标题翻译：多端口存储设备中的端口间通信
公开(公告)号：US07949863B2
公开(公告)日：2011-05-24
申请号：US11694819
申请日：2007-03-30
申请人： Alan T. Ruberg , Dae Kyeung Kim , Daeyun Shim , Dongyun Lee , Myung Rai Cho , Sungjoon Kim
发明人： Alan T. Ruberg , Dae Kyeung Kim , Daeyun Shim , Dongyun Lee , Myung Rai Cho , Sungjoon Kim
IPC分类号： G06F9/48 , G06F15/76
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
摘要翻译：一种利用多端口存储器件进行端口间通信的方法和系统。存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时，第一组件将消息写入与第二端口相关联的消息缓冲器。第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。然后第二个组件从消息缓冲区读取消息。

2. 发明授权

US07639561B2 Multi-port memory device having variable port speeds 有权
标题翻译：具有可变端口速度的多端口存储设备
公开(公告)号：US07639561B2
公开(公告)日：2009-12-29
申请号：US11694813
申请日：2007-03-30
申请人： Dongyun Lee , Myung Rai Cho , Sungjoon Kim
发明人： Dongyun Lee , Myung Rai Cho , Sungjoon Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储体。每个端口都应用两个时钟信号：系统时钟和端口时钟。系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。端口时钟应用于与每个端口相关联的时钟分频器电路。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

3. 发明授权

US07831778B2 Shared nonvolatile memory architecture 有权
标题翻译：共享非易失性存储器架构
公开(公告)号：US07831778B2
公开(公告)日：2010-11-09
申请号：US11690629
申请日：2007-03-23
申请人： Myung Rai Cho , Dongyun Lee , Alan Ruberg
发明人： Myung Rai Cho , Dongyun Lee , Alan Ruberg
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.
摘要翻译：一种利用共享非易失性存储器来初始化设备中的多个处理组件的方法和系统。用于处理设备内的组件的启动逻辑和配置数据存储在单个非易失性存储器中。在接收到用于初始化设备的命令时，共享存储器系统将启动逻辑和配置数据从非易失性存储器复制到易失性主存储器。然后，每个处理组件访问主存储器以找到其启动逻辑和配置数据并开始执行。共享存储器系统减少用于初始化多个处理组件的非易失性存储器组件的数量。

4. 发明授权

US08160192B2 Signal interleaving for serial clock and data recovery 有权
标题翻译：信号交错用于串行时钟和数据恢复
公开(公告)号：US08160192B2
公开(公告)日：2012-04-17
申请号：US11861175
申请日：2007-09-25
申请人： Dongyun Lee , Sungjoon Kim
发明人： Dongyun Lee , Sungjoon Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812
摘要： A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.
摘要翻译：一种用于从串行数据流中恢复定时信息和数据的时钟和数据恢复（CDR）系统和方法。 CDR系统包括产生恢复的时钟/数据信号的采样电路和向采样电路提供反馈的交错反馈网络。反馈网络包括基于恢复的时钟/数据信号产生控制信号的逻辑电路，第一多路复用器，其基于控制信号从全局时钟信号的四相中选择第一延迟锁定环，第一延迟锁定环具有第一组延迟单元，耦合到第二多路复用器，其基于所选择的全局时钟信号产生延迟的信号;以及第二延迟锁定环，其具有产生一组相移反馈信号的第二组延迟单元，所述相移反馈信号被施加到采样电路使采样电路与接收到的串行数据流中的转换相对齐。

5. 发明授权

US08407427B2 Method and system for improving serial port memory communication latency and reliability 有权
标题翻译：提高串口存储器通信延迟和可靠性的方法和系统
公开(公告)号：US08407427B2
公开(公告)日：2013-03-26
申请号：US12605134
申请日：2009-10-23
申请人： Alan Ruberg , Seoung Jeong Lee , Hyung Rok Lee , Daeyun Shim , Dongyun Lee , Sungjoon Kim , Anu Murthy
发明人： Alan Ruberg , Seoung Jeong Lee , Hyung Rok Lee , Daeyun Shim , Dongyun Lee , Sungjoon Kim , Anu Murthy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C7/1075 , G06F11/141 , G06F11/1443 , G06F13/1663 , G06F13/4234 , G11C5/066 , Y02D10/14 , Y02D10/151
摘要： A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
摘要翻译：公开了一种用于减少存储器延迟的方法，装置和系统。在一个实施例中，主计算机系统和存储器之间的数据经由多个时间间隔上的存储器端口或一组端口进行通信，其中主计算机耦合到存储器。此外，与数据相关联的命令在主计算机系统和存储器之间通过端口或端口组通过单个时间间隔进行通信。

6. 发明申请

US20080235528A1 PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE 有权
标题翻译：多端口存储器件的逐步功率控制
公开(公告)号：US20080235528A1
公开(公告)日：2008-09-25
申请号：US11690642
申请日：2007-03-23
申请人： Sungjoon Kim , Dongyun Lee , Edward Kim
发明人： Sungjoon Kim , Dongyun Lee , Edward Kim
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1075 , G11C7/22 , Y02D10/14 , Y02D50/20
摘要： A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.
摘要翻译：提供了一种逐渐降低串行存储设备的功耗的方法和系统，称为功率控制系统。电源控制系统监视多端口串行存储器的端口，以便可以在每个端口的基础上启用或禁用它们。当在端口上没有发送或接收数据时，采取一系列步骤逐步取消对端口的部分断电并使端口进入低功率状态。通过禁用某些端口并将端口置于低功耗状态，整个串行端口存储器的功耗显着降低。

7. 发明授权

US07908501B2 Progressive power control of a multi-port memory device 有权
标题翻译：多端口存储设备的逐行功率控制
公开(公告)号：US07908501B2
公开(公告)日：2011-03-15
申请号：US11690642
申请日：2007-03-23
申请人： Sungjoon Kim , Dongyun Lee , Edward Kim
发明人： Sungjoon Kim , Dongyun Lee , Edward Kim
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1075 , G11C7/22 , Y02D10/14 , Y02D50/20
摘要： A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.
摘要翻译：提供了一种逐渐降低串行存储设备的功耗的方法和系统，称为功率控制系统。电源控制系统监视多端口串行存储器的端口，以便可以在每个端口的基础上启用或禁用它们。当在端口上没有发送或接收数据时，采取一系列步骤逐步取消对端口的部分断电并使端口进入低功率状态。通过禁用某些端口并将端口置于低功耗状态，整个串行端口存储器的功耗显着降低。

8. 发明申请

US20080075222A1 SIGNAL INTERLEAVING FOR SERIAL CLOCK AND DATA RECOVERY 有权
标题翻译：用于串行时钟和数据恢复的信号交互
公开(公告)号：US20080075222A1
公开(公告)日：2008-03-27
申请号：US11861175
申请日：2007-09-25
申请人： Dongyun Lee , Sungjoon Kim
发明人： Dongyun Lee , Sungjoon Kim
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812
摘要： A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.
摘要翻译：一种用于从串行数据流中恢复定时信息和数据的时钟和数据恢复（CDR）系统和方法。 CDR系统包括产生恢复的时钟/数据信号的采样电路和向采样电路提供反馈的交错反馈网络。反馈网络包括基于恢复的时钟/数据信号产生控制信号的逻辑电路，第一多路复用器，其基于控制信号从全局时钟信号的四相中选择第一延迟锁定环，第一延迟锁定环具有第一组延迟单元，耦合到第二多路复用器，其基于所选择的全局时钟信号产生延迟的信号;以及第二延迟锁定环，其具有产生一组相移反馈信号的第二组延迟单元，所述相移反馈信号被施加到采样电路使采样电路与接收到的串行数据流中的转换相对齐。

9. 发明申请

US20100106917A1 METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY 有权
标题翻译：改进串口存储器通信延迟和可靠性的方法和系统
公开(公告)号：US20100106917A1
公开(公告)日：2010-04-29
申请号：US12605134
申请日：2009-10-23
申请人： Alan Ruberg , Seoung Jeong Lee , Hyung Rok Lee , Daeyun Shim , Dongyun Lee , Sungjoon Kim , Anu Murthy
发明人： Alan Ruberg , Seoung Jeong Lee , Hyung Rok Lee , Daeyun Shim , Dongyun Lee , Sungjoon Kim , Anu Murthy
IPC分类号： G06F12/10
CPC分类号： G11C7/1075 , G06F11/141 , G06F11/1443 , G06F13/1663 , G06F13/4234 , G11C5/066 , Y02D10/14 , Y02D10/151
摘要： A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
摘要翻译：公开了一种用于减少存储器延迟的方法，装置和系统。在一个实施例中，主计算机系统和存储器之间的数据经由多个时间间隔上的存储器端口或一组端口进行通信，其中主计算机耦合到存储器。此外，与数据相关联的命令在主计算机系统和存储器之间通过端口或端口组通过单个时间间隔进行通信。

10. 发明申请

US20070245094A1 MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 有权
标题翻译：具有可变端口速度的多端口存储器件
公开(公告)号：US20070245094A1
公开(公告)日：2007-10-18
申请号：US11694813
申请日：2007-03-30
申请人： Dongyun Lee , Myung Cho , Sungjoon Kim
发明人： Dongyun Lee , Myung Cho , Sungjoon Kim
IPC分类号： G06F13/00
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储器组。每个端口都应用两个时钟信号：系统时钟和端口时钟。系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。端口时钟应用于与每个端口相关联的时钟分频器电路。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

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