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    • 3. 发明申请
    • UNIT FOR DISPLAYING ACCELERATION FOR TRAVELING APPARATUS
    • 显示用于行驶装置加速度的装置
    • US20110093156A1
    • 2011-04-21
    • US12908044
    • 2010-10-20
    • Hyung-Rok LEESeung-Hee LEE
    • Hyung-Rok LEESeung-Hee LEE
    • G06F7/00
    • B60Q1/54B60Q1/44B60Q1/441
    • Provided is a unit for displaying acceleration for a traveling apparatus. The unit for displaying acceleration for a traveling apparatus includes a sensor installed on an acceleration pedal operating to control a traveling speed of the traveling apparatus, and sensing operation of the acceleration pedal to transmit electric signal to the outside, and a light emission control module installed in the traveling apparatus, receiving the electric signal from the sensor and controlling light emission of one or a plurality of first lamps installed around taillights of the traveling apparatus. Therefore, when a driver presses an acceleration pedal while driving a traveling apparatus, an acceleration state of the traveling apparatus may be displayed to the outside to inform the state.
    • 提供了用于显示行驶装置的加速度的单元。 用于显示行驶装置的加速度的单元包括安装在加速踏板上的传感器,其操作用于控制行驶装置的行进速度,以及感测加速踏板的操作以将电信号传输到外部,并且安装有发光控制模块 在行进装置中,从传感器接收电信号,控制安装在行驶装置的尾灯附近的一个或多个第一灯的发光。 因此,当驾驶者在驾驶行驶装置的同时按下加速踏板时,可以向外部显示行驶装置的加速状态,以通知该状态。
    • 4. 发明授权
    • Phase lock loop with coarse control loop having frequency lock detector and device including same
    • 具有粗调控制回路的锁相环具有频率锁定检测器和包括其的装置
    • US07102446B1
    • 2006-09-05
    • US11056995
    • 2005-02-11
    • Hyung-Rok LeeMoon-Sang HwangSang-Hyun LeeBong-Joon LeeDeog-Kyoon Jeong
    • Hyung-Rok LeeMoon-Sang HwangSang-Hyun LeeBong-Joon LeeDeog-Kyoon Jeong
    • H03L7/07H03L7/087H04B1/40H04B1/50
    • H03L7/087H03K23/507H03L7/089H03L7/093H03L7/099H03L7/0995H03L7/10H03L2207/06H04L7/0337Y10S331/02
    • A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.
    • 用于控制采样时钟或其他时钟的锁相环(PLL)以及数据采样电路,收发器或包括这种PLL的其它装置。 PLL包括多范围VCO,用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。 粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。 通常,当VCO输出时钟频率和参考频率之间的差减小到预定阈值时,频率锁定检测器锁定粗略控制环路的操作,而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率 当VCO的精细控制电压离开预定范围时的电压特性。 其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器(包括至少两个接收器接口和发射器接口),以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL(用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL)。 每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样,并且数字电路包括接收过采样数据的多层数字锁相环电路。